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f71806 july, 2007 v0.26p f71806 F71806F/fg super h/w monitor + lpc io release date: july, 2007 revision: v0.26p
f71806 july, 2007 v0.26p f71806 f71806 datasheet revision history version date page revision history 0.10p 10/04/2004 - preliminary release version. 0.20p 10/27/2004 - added application circuit. 0.21p 04/15/2005 - added ?green package? ordering information 0.22p 11/01/2005 - added 24mhz clock input. - updated application circuit. - after v0.22p datasheet is for b version chip use and downward compatible. 0.23p 11/20/2005 - added ovt# signal output in pin 55. - modified pin 77 ovt# function to be the default function. 0.24p 12/08/2005 - modified datasheet revi sion history description of version 0.22p/0.23p. (for lbb version use after v0.22p) 0.25p 12/28/2006 added patent note 0.26p 07/05/2007 - company readdress please note that all data and specifications are subject to change without notice. all the trade marks of products and companies mentioned in this data sheet belong to their respective owners. life support applications these products are not designed for use in life support app liances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. customers using or selling these products for use in such applications do so at their own risk and agree to fu lly indemnify fintek for any damages resulting from such improper use or sales.
july, 2007 v0.26p 1 f71806 table of contents 1 general description ............................................................................................................ .............................................4 2 features ....................................................................................................................... .............................................................4 3 key specif ications ............................................................................................................. .................................................6 4 pin configuration.............................................................................................................. .................................................6 5 pin descriptions ............................................................................................................... ....................................................7 5.1 p ower p in ............................................................................................................................... ..........................................7 5.2 lpc i nterface ............................................................................................................................... ..................................7 5.3 fdc ............................................................................................................................ .......................................................8 5.4 uart p ort and sir............................................................................................................................ .............................8 5.5 ieee 1284 p arallel p ort ............................................................................................................................... ..............10 5.6 h/w m onitor ............................................................................................................................... ..................................11 5.7 acpi function pins ............................................................................................................................... ........................12 5.8 vid controlling pins ............................................................................................................................... ....................13 5.9 n.c pins ............................................................................................................................... ............................................13 6 function description ........................................................................................................... ..........................................14 6.1 p ower on s trapping o ptions ............................................................................................................................... ........14 6.2 acpi........................................................................................................................... .....................................................14 6.3 pci r eset and pwrok s ignals ............................................................................................................................... ...15 6.4 h ardware m onitor ............................................................................................................................... .......................16 6.5 fdc ............................................................................................................................ .....................................................23 6.6 uart ........................................................................................................................... ...................................................23 6.7 p arallel p ort ............................................................................................................................... ................................23 7 register descriptions.......................................................................................................... ..........................................24 7.1 g lobal c ontrol r egisters ............................................................................................................................... ..........24 7.1.1 software reset register ? inde x 02h..................................................................................................................... ................... 25 7.1.2 logic device number register ? index 07h..................................................................................................................... ........ 25 7.1.3 chip id register ? inde x 20h ..................................................................................................................... .............................. 25 7.1.4 chip id register ? inde x 21h ..................................................................................................................... .............................. 25 7.1.5 vendor id register ? index 23h ..................................................................................................................... .......................... 25 7.1.6 vendor id register ? index 24h ..................................................................................................................... .......................... 26 7.1.7 software power down register ? index 25h ..................................................................................................................... ....... 26
july, 2007 v0.26p 2 f71806 7.1.8 uart irq sharing register ? inde x 26h ..................................................................................................................... ........... 26 7.1.9 power led function select register ? index 28h.................................................................................................................... 2 7 7.1.10 multi function select 1 register ? index 29h (pow ered by vdd) ........................................................................................... 28 7.1.11 multi function select 2 register ? index 2ah (pow ered by vdd) .......................................................................................... 29 7.1.12 multi function select 3 register ? index 2bh (pow ered by vdd) .......................................................................................... 29 7.1.13 multi function select 4 register ? index 2ch (power ed by vsb3v) ...................................................................................... 30 7.1.14 multi function select 5 register ? index 2dh (power ed by vsb3v)...................................................................................... 31 7.2 fdc r egisters ............................................................................................................................... ................................32 7.2.1 logic device number register................................................................................................... ................................................. 32 7.2.2 fdc configurati on registers.................................................................................................... ................................................... 32 7.2.3 device registers ............................................................................................................... ........................................................... 35 7.3 uart1 r egisters ............................................................................................................................... ...........................50 7.3.1 logic device number register................................................................................................... ................................................. 50 7.3.2 uart 1 configura tion registers ................................................................................................. ................................................ 50 7.3.3 device registers ............................................................................................................... ........................................................... 51 7.4 uart 2 r egisters ............................................................................................................................... ..........................54 7.4.1 logic device number register................................................................................................... ................................................. 54 7.4.2 uart 2 configura tion registers ................................................................................................. ................................................ 55 7.4.3 device registers ............................................................................................................... ........................................................... 56 7.5 p arallel p ort r egisters ............................................................................................................................... ..............60 7.5.1 logic device number register................................................................................................... ................................................. 60 7.5.2 parallel port conf iguration register ........................................................................................... ................................................. 60 7.5.3 device registers ............................................................................................................... ........................................................... 61 7.6 h ardware m onitor r egisters ............................................................................................................................... .....65 7.6.1 logic device number register................................................................................................... ................................................. 65 7.6.2 hardware monitor conf iguration re gisters ....................................................................................... .......................................... 66 7.6.3 device registers ............................................................................................................... ........................................................... 67 7.7 gpio r egisters ............................................................................................................................... ..............................85 7.7.1 logic device number register................................................................................................... ................................................. 85 7.7.2 configuration registers ........................................................................................................ ....................................................... 85 7.8 vid r egister ............................................................................................................................... ..................................93 7.8.1 logic device number register................................................................................................... ................................................. 93 7.8.2 vid configurati on registers .................................................................................................... ................................................... 94 7.8.3 device registers ............................................................................................................... ........................................................... 94 7.9 acpi and pme r egisters ............................................................................................................................... ..............97 7.9.1 logic device number register................................................................................................... ................................................. 97 7.9.2 acpi and pme confi guration registers........................................................................................... ........................................... 97
july, 2007 v0.26p 3 f71806 8 pcb layout guide............................................................................................................... .................................................99 9 electrical char acteristics ..................................................................................................... ..............................101 9.1 a bsolute m aximum r at i n g s ............................................................................................................................... ......101 9.2 dc c haracteristics ............................................................................................................................... ....................102 9.3 ac c haracteristics ............................................................................................................................... ....................102 10 ordering information ........................................................................................................... ...................................103 11 package dimensions............................................................................................................. .......................................103 12 f71806 demo circuit ............................................................................................................ ..........................................104
july, 2007 v0.26p 4 f71806 1 general description the f71806 is the featured io chip without kbc f unction specifically for clone chipset pc system. equipped with one ieee 1284 parallel port , two uart port and fdc. the f71806 pr ovides sir, integrated with hardware monitor, supports 11 sets of voltage sens or and 4 voltage fault signal outputs, 3 sets of creative auto-controlling fans and 3 temperature sensor pins for the accurate current type temp. measurement for cpu thermal diode or external transistors 2n3906. the f71806 provides flexible featur es for multi-directional applicati on. for instance, supports 12 pins cpu vid controlling for vrm9.0/10.0 and cpu vid otf (o n the fly), provides 24 gpio pins which include pulse/level mode selection, irq sharing function also designed in uart feature for particular usage and accurate current mode h/w monitor will be worth in meas urement of temperature, pr ovides 3 modes fan speed control mechanism included manual mode/speed mode/temper ature mode for users? selection. the f71806 is powered by 3.3v voltage, with the lp c interface in the package of 128-qfp. 2 features general functions ? comply with lpc spec. 1.0 ? support dpm (device power management), acpi ? support 12 pins cpu vid controlling and comply with vrm9.0/10.0 ? vcore monitoring supports dynamic vid ? 24 gpio pins for flexible application ? 24/48 mhz clock input fdc ? compatible with ibm pc at disk drive systems ? variable write pre-compensation with track selectable capability ? support vertical recording format ? dma enable logic ? 16-byte data fifos ? support floppy disk drives and tape drives ? detects all overrun and under run conditions ? built-in address mark detection circuit to simplify the read electronics ? completely compatible with industry standard 82077 ? 360k/720k/1.2m/1.44m/2.88m format; 250k, 300k, 500k, 1m, 2m bps data transfer rate
july, 2007 v0.26p 5 f71806 uart ? two high-speed 16c550 compatible uart with 16-byte fifos ? fully programmable serial-interface characteristics ? baud rate up to 115.2k infrared ? support irda version 1.0 sir protocol with maximum baud rate up to 115.2k bps parallel port ? one ps/2 compatible bi-directional parallel port ? support enhanced parallel port (epp) ? compatible with ieee 1284 specification ? support extended capabilities port (ecp) ? compatible with ieee 1284 specification ? enhanced printer port back-drive current protection hardware monitor functions ? 12 vid pins for vrm10.0 and cpu vid otf (on the fly) ? 3 current type accurate ( 3) j thermal inputs for cpu thermal diode and 2n3906 transistors ? 11 sets voltage monitoring (8 external and 3 internal powers) ? 4 voltage_fault# hardware signal outputs ? 3 fan speed monitoring inputs ? 3 fan speed auto-control (support 3 wire and 4 wire fans) ? case intrusion detection circuit ? watchdog comparison of all monitored values ? issue pme# and independent voltage_fault # package ? 128-pin pqfp noted: patented tw207103 tw207104 us6788131 b1 tw235231 tw237183 twi263778
july, 2007 v0.26p 6 f71806 3 key specifications supply voltage 3.0v to 3.6v operating supply current 16 ma typ. 4 pin configuration
july, 2007 v0.26p 7 f71806 5 pin descriptions i/o 12t - ttl level bi-directional pin with 12 ma source-sink cap ability. i/ood 12t i/ood 16t - ttl level bi-directional pin, can select to od or out by register, with 12 ma source-sink capability. - ttl level bi-directional pin, can select to od or out by register, with 16 ma source-sink capability. i/od 12t i/od 12ts5v i/o 12ts5v i/od 16t,5v i/o 8t-u47,5v - ttl level bi-directional pin, open-drain outpu with 12 ma sink capability. - ttl level bi-directional pin and schmitt trigger, open-drain output with 12 ma sink capability, 5v tolerance. - ttl level bi-directional pin and schmitt trigger with 12 ma sink capability, 5v tolerance. - ttl level bi-directional pin, open-drain outpu with 16 ma sink capability, 5v tolerance. - ttl level bi-directional pin with 8 ma sink capability, pull-up 47k ohms, 5v tolerance. o 12 - output pin with 12 ma source-sink capability. aout - output pin(analog). od 12 od 16-u10,5v od 24 - open-drain output pin with 12 ma sink capability. - open-drain output pin with 16 ma sink ca pability, pull-up 10k ohms, 5v tolerance. - open-drain output pin with 24 ma sink capability. in t5v in ts - ttl level input pin,5v tolerance. - ttl level input pin and schmitt trigger. in ts5v - ttl level input pin and schmitt trigger, 5v tolerance. ain - input pin(analog). p - power. 5.1 power pin pin no. pin name type description 4,35,99 vcc p power supply voltage input with 3.3v 67 vsb p stand-by power supply voltage input 3.3v 69 vbat p battery voltage input 86 agnd(d-) p analog gnd 15,50,74, 117 gnd p digital gnd 5.2 lpc interface pin no. pin name type pwr description 37 lreset# in ts vcc reset signal. it can connect to pcirst# signal on the host.
july, 2007 v0.26p 8 f71806 38 ldrq# o 12 vcc encoded dma request signal. 39 serirq i/o 12t vcc serial irq input/output. 40 lfram# in ts vcc indicates start of a new cycle or termination of a broken cycle. 41-44 lad[3:0] i/o 12t vcc these signal lines communicate address, control, and data information over the lpc bus between a host and a peripheral. 47 pciclk in ts vcc 33mhz pci clock input. 49 clkin in ts vcc system clock input. according to the input frequency 24/48mhz. 5.3 fdc pin no. pin name type pwr description 51 densel# od 24 vcc drive density select. set to 1 - high data rate.(500kbps, 1mbps) set to 0 ? low data rate. (250kbps, 300kbps) 52 moa# od 24 vcc motor a on. when set to 0, this pin enables disk drive 0. this is an open drain output. 54 drva# od 24 vcc drive select a. when set to 0, this pin enables disk drive a. this is an open drain output. 56 wdata# od 24 vcc write data. this logic low open drain writes pre-compensation serial data to the selected fdd. an open drain output. 57 dir# od 24 vcc direction of the head step motor. an open drain output. logic 1 = outward motion logic 0 = inward motion 58 step# od 24 vcc step output pulses. this active low open drain output produces a pulse to move the head to another track. 59 hdsel# od 24 vcc head select. this open dr ain output determines which disk drive head is active. logic 1 = side 0 logic 0 = side 1 60 wgate# od 24 vcc write enable. an open drain output. 61 rdata# in ts5v vcc the read data input signal from the fdd. 62 trk0# in ts5v vcc track 0. this schmitt-tri ggered input from the disk drive is active low when the head is pos itioned over the outermost track. 63 index# in ts5v vcc this schmitt-triggered input fr om the disk drive is active low when the head is positioned over the beginning of a track marked by an index hole. 64 wpt# in ts5v vcc write protected. this active low schmitt input from the disk drive indicates that the diske tte is write-protected. 65 dskchg# in ts5v vcc diskette change. this signal is active low at power on and whenever the diskette is removed. 5.4 uart port and sir pin no. pin name type pwr description
july, 2007 v0.26p 9 f71806 o 12 infrared transmitter output. 66 irtx/gpio16 i/o 12t vcc general purpose io in ts infrared receiver input. 70 irrx/gpio30 i/ood 12t vsb general purpose io. open drain a nd drive select by register. 118 dcd1# in t5v vcc data carrier detect. an active low signal indicates the modem or data set has detected a data carrier. 119 ri1# in t5v vcc ring indicator. an active low signal indicates that a ring signal is being received from the modem or data set. 120 cts1# in t5v vcc clear to send is the modem control input. 121 dtr1# i/o 8t-u47,5v vcc uart 1 data terminal ready. an active low signal informs the modem or data set that controller is ready to communicate. internal 47k ohms pulled high and disable after power on strapping. 122 rts1# i/o 8t-u47,5v vcc uart 1 request to send. an active low signal informs the modem or data set that the contro ller is ready to send data. internal 47k ohms pulled high and disable after power on strapping. 123 dsr1# in t5v vcc data set ready. an active low signal indicates the modem or data set is ready to establish a communication link and transfer data to the uart. uart 1 serial output. used to transmit serial data out to the communication link. internal 47k ohms pulled high and disable after power on strapping. 124 sout1/ config4e_2e i/o 8t-u47,5v vcc power on strapping : 1 (default) c onfiguration register:4e 0 c onfiguration register:2e 125 sin1 in t5v vcc serial input. used to receive serial data through the communication link. 126 dcd2# in t5v vcc data carrier detect. an active low signal indicates the modem or data set has detected a data carrier. 127 ri2# in t5v vcc ring indicator. an active low signal indicates that a ring signal is being received from the modem or data set. 128 cts2# in t5v vcc clear to send is the modem control input. uart 2 data terminal ready. an active low signal informs the modem or data set that controller is ready to communicate. internal 47k ohms pulled high and disable after power on strapping. 1 dtr2# / rst_drv i/o 8t-u47,5v vcc power on strapping : 1 (default) : pin31/33/34/48/84 od 0 drive uart 2 request to send. an active low signal informs the modem or data set that the contro ller is ready to send data. internal 47k ohms pulled high and disable after power on strapping. 2 rts2#/pwm_dc i/o 8t-u47,5v vcc power on strapping : 1 (default) pwm mode 0 drive linear mode 3 dsr2# in t5v vcc data set ready. an active low signal indicates the modem or data set is ready to establish a communication link and transfer data to the uart. 5 sout2 i/o 8t-u47,5v vcc uart 2 serial output. used to transmit serial data out to the communication link. internal 47k ohms pulled high and disable after power on strapping. 6 sin2 in t5v vcc serial input. used to receive serial data through the communication link.
july, 2007 v0.26p 10 f71806 5.5 ieee 1284 parallel port pin no. pin name type pwr description 100 slct in ts5v vcc an active high input on this pin indicates that the printer is selected. refer to the description of the parallel port for definition of this pin in ecp and epp mode. 101 pe in ts5v vcc an active high input on this pin indicates that the printer has detected the end of the paper. re fer to the description of the parallel port for the definition of this pin in ecp and epp mode. 102 busy in ts5v vcc an active high input indicate s that the printer is not ready to receive data. refer to the description of the parallel port for definition of this pin in ecp and epp mode. 103 ack# in ts5v vcc an active low input on this pin indicates that the printer has received data and is ready to accept more data. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. 104 slin# i/od 12ts5v vcc output line for detection of pr inter selection. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. 105 init# i/od 12ts5v vcc output line for the printer initialization. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. 106 err# in ts5v vcc an active low input on this pin indicates that the printer has encountered an error condition. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. 107 afd# i/od 12ts5v vcc an active low output from this pin causes the printer to auto feed a line after a line is printed. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. 108 stb# i/od 12ts5v vcc an active low output is used to latch the parallel data into the printer. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. 109 pd0 i/o 12ts5v vcc parallel port data bus bit 0. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. 110 pd1 i/o 12ts5v vcc parallel port data bus bit 1. 111 pd2 i/o 12ts5v vcc parallel port data bus bit 2. 112 pd3 i/o 12ts5v vcc parallel port data bus bit 3. 113 pd4 i/o 12ts5v vcc parallel port data bus bit 4. 114 pd5 i/o 12ts5v vcc parallel port data bus bit 5. 115 pd6 i/o 12ts5v vcc parallel port data bus bit 6. 116 pd7 i/o 12ts5v vcc parallel port data bus bit 7.
july, 2007 v0.26p 11 f71806 5.6 h/w monitor pin no. pin name type pwr description atx power good. 95 atxpg/vin4 ain vcc voltage input 4. pci reset # signal input. 91 pcirstin#/vin8 ain vcc voltage input 8. 92-94, vin7~vin5 ain vcc voltage input 7 ~ 5. 96-98 vin3~vin1 ain vcc voltage input 3 ~ 1. 7 fanin1 in ts vcc fan 1 tachometer input. 8 fan_ctl1 o 12 vcc fan 1 control output. this pin provides pwm duty-cycle output or a voltage output. 9 fanin2 in ts vcc fan 2 tachometer input. 10 fan_ctl2 o 12 vcc fan 2 control output. this pin provides pwm duty-cycle output or a voltage output. 11 fanin3 in ts vcc fan 3 speed input. 12 fan_ctl3 o 12 vcc fan 3 control output. this pin provides pwm duty-cycle output or a voltage output. 87 d3+ ain vcc cpu thermal diode/trans istor temperature sensor input. 88 d2+ ain vcc cpu thermal diode/transis tor temperature sensor input. 89 d1+ ain vcc cpu thermal diode/transis tor temperature sensor input. 90 vref aout vcc voltage sensor output. generated pme event. it supports the pci pme# interface. this signal allows the peripheral to request the system to wake up from the s3 state. 73 pme#/gpio21 od 12 i/od 12t vsb general purpose io. 26 gpio0 i/ood 12t vcc general purpose io. 1. support level and pulse mode output. 2. open drain and drive select 3. without input de-bounce. 27 gpio1 i/ood 12t vcc general purpose io. 1. support level and pulse mode output. 2. open drain and drive select 3. without input de-bounce. 28 gpio2 i/ood 12t vcc general purpose io. 1. support level and pulse mode output. 2. open drain and drive select 3. without input de-bounce. general purpose io. 1. support level and pulse mode output. 2. open drain and drive select 3. without input de-bounce. voltage fault indication for vin1 abnormal event. 29 gpio3/ voltage_fault1#/ irrx i/ood 12t vcc infrared receiver input. (powered by vcc) 36 gpio4/ voltage_fault2#/ beep i/ood 12t vcc general purpose io. 1. support level and pulse mode output. 2. open drain and drive select 3. without input de-bounce.
july, 2007 v0.26p 12 f71806 voltage fault indication for vin2 abnormal event. beep pin. general purpose io. 1. support level and pulse mode output. 2. open drain and drive select 3. without input de-bounce. voltage fault indication for vin3 abnormal event. 53 gpio5/ voltage_fault3#/ fanctl1 i/ood 12t vcc fan 1 control output. this pin provides pwm duty-cycle open drain output for intel 4-pin fan. general purpose io. 1. support level and pulse mode output. 2. open drain and drive select 3. without input de-bounce. voltage fault indication for vin4 abnormal event. watch dog timer signal output 1. 55 gpio6/ voltage_fault4#/ wdtrst1#/ ovt# i/ood 12t vcc over temperature signal output. over temperature signal output.(default 85 x c) general purpose io. open drain a nd drive select by register. 77 ovt#/ gpio24/ wdtrst2# i/ood 12t vsb watch dog timer signal output 2. 5.7 acpi function pins pin no. pin name type pwr description reset connect# with 50ms debouce function, it connects to reset button, and also other reset source on the motherboard. if the register rstc on_en (5h) is set to 1, the pin 30 will infect pcirst1# ~ pcirst5# outcome. if the register rstcon_en is set to 0, the pin 30 will infect pwrok1 and pwrok2 outcome. 30 rstcon#/gpio10 i/od 12t vcc general purpose io. it is a output buffer of rstcon# and lreset#. 31 pcirst1#/gpio11 i/ood 16t vcc general purpose io. pin1 rst_drv = 1(high) : od = 0(low) : drive pwrok function, it is power good signal of vcc, which is delayed 400ms (default) as vcc arrives at 2.8v. 32 pwrok1/gpio12 i/od 12t vcc general purpose io. it is a output buffer of rstcon# and lreset#. 33 pcirst2#/gpio13 i/ood 16t vcc general purpose io. pin1 rst_drv = 1(high) : od =0(low): drive it is a output buffer of rstcon# and lreset#. 34 pcirst3#/gpio14 i/ood 16t vcc general purpose io. pin1 rst_drv = 1(high) : od =0(low) : drive it is a output buffer of rstcon#,lreset# and pcirstin. 48 pcirst5#/gpio15 led_vcc i/ood 16t vcc general purpose io. pin1 rst_drv = 1(high) : od =0(low) : drive
july, 2007 v0.26p 13 f71806 power led for vcc. 68 copen# in t vbat case open detection #. this pin is connected to a specially designed low power cmos flip-flop backed by the battery for case open state preservation during power loss. in t s3# input is main power on-off switch input. 71 s3#/gpio31 i/od 12t vsb general purpose io. od 12 vsb panel switch output. this pin is low active and pulse output. it is power on request output#. 72 pwswout# /gpio20 i/od 12t general purpose io. in t main power switch button input. 75 pwswin# /gpio22 i/od 12t vsb general purpose io. od 12 vsb power supply on-off control output. connect to atx power supply ps_on# signal. 76 pson#/gpio23 i/od 12t general purpose io. pwrok function, it is power good signal of vcc, which is delayed 400ms (default) as vcc arrives at 2.8v. general purpose io. 78 pwrok2/gpio25/ led_vsb i/od 12t vsb power led for vsb it is a output buffer of rstcon#,lreset# and pcirstin. 84 pcirst4#/gpio26 i/ood 16t vsb general purpose io. pin1 rst_drv = 1(high) : od =0(low) : drive resume reset# function, it is power good signal of vsb, which is delayed 66ms as vsb arrives at 2.3v. 85 rsmrst#/gpio27 i/od 12t vsb general purpose io. 5.8 vid controlling pins pin no. pin name type pwr description 13,14, 16,17, 18,19 vidin[5:0] in ts vcc cpu vid input pins. 1. special level input vih ? 0.9, vil ? 0.6. 2. power by vcc. 20-25 vidout[5:0] od 12 vcc cpu vid output pins. 79 slotocc# in ts vsb cpu slotocc# input. 5.9 n.c pins pin no. pin name description 45,46,80,81,82,83 n.c n.c pins
july, 2007 v0.26p 14 f71806 6 function description 6.1 power on strapping options the f71806 provides four pins for power on hardware strapping to select functions. there is a form to describe how to set the functions you want. pin no. symbol value description 1 pin31/33/34/48/84 will be defined a open drain pin. (default) 1 rst_drv 0 pin31/33/34/48/84 will be defined a drive pin. 1 fan control mode: pwm mode. ( default) 2 pwm_dc 0 fan control mode: linear mode. 1 chip selection in configuration 4e. (default) 124 config4e_2e 0 chip selection in configuration 2e. 6.2 acpi the advanced configuration and power interface (acpi) is a system for controlling the use of power in a computer. it lets computer manufacturer and user to determine the computer?s power usage dynamically. there are three acpi states that are of primary conc ern to the system designer and they are designated s0, s3 and s5. s0 is a full-power state; the computer is being actively used in this state. the other two are called sleep states and reflect different power consumption when power-down. s3 is a stat e that the processor is powered down but the last procedural st ate is being stored in memory which is still active. s5 is a state that memory is off and the last procedural state of the proc essor has been stored to the hard disk. take s3 and s5 as comparison, since memory is fast, the computer can qui ckly come back to full-power state, the disk is slower than the memory and the computer takes longer time to come back to full-power state. however, since the memory is off, s5 draws the minimal power comparing to s0 and s3. it is anticipated that only the following state transitions may happen: s0 ? s3, s0 ? s5, s5 ? s0, s3 ? s0 and s3 ? s5. among them, s3 ? s5 is illegal transition and won?t be allowed by st ate machine. it is necessary to enter s0 first in order to get to s5 from s3. as for transition s5 ? s3 will occur only as an i mmediate state during state transition from s5 ? s0. it isn?t allowed in the normal state transition. the below diagram described the timing, the always on and always off, keep last state could be set in control register. in keep last state mode, one register will keep the status of before power loss. if it is power on
july, 2007 v0.26p 15 f71806 before power loss, it will remain power on when power is re sumed, otherwise, if it is power off before power loss, it will remain power off when power is resumed. vbat vsb rsmrst# s3# ps_on# psin# psout# vcc3v default timing always off vbat vsb rsmrst# s3# ps_on# psin# psout# vcc3v always on timing 6.3 pci reset and pwrok signals the f71806 supports 5 output buffers for 5 reset signals. if the register rstcon_en (5h) is set to 1, the pin rstcon# will infect pcirst1# ~ pcirst5# outcome. then, the result of pcirst# outcome will be affected by conditions
july, 2007 v0.26p 16 f71806 as below: pcirst1# ? output buffer of rstcon# and lreset#. pcirst2# ? output buffer of rstcon# and lreset#. pcirst3# ? output buffer of rstcon# and lreset#. pcirst4# ? output buffer of rstcon#, lreset# and pcirstin# pcirst5# ? output buffer of rstcon#, lreset# and pcirstin# delay +3.3v s3# atxpg rstcon# pwrok1/2 rstcon# lreset# pcirst1~3# pcirstin# pcirst4~5# delay +3.3v s3# atxpg rstcon# pwrok1/2 rstcon# lreset# pcirst1~3# pcirstin# pcirst4~5# so far as the pwrok issue is as above figure. pw rok is delayed 400ms (default) as vcc arrives 2.8v, and the delay timing can be programmed by register. (100ms ~ 400ms) in the figure, the rstcon# will be implemented by regi ster rstcon_en. if rstcon_en be set to 0, the rstcon# pin will affect pwrok outpu ts. if rstcon_en be set to 1, the rstcon# pin will affect pcirst outputs (default). 6.4 hardware monitor 6.4.1 analog input the f71806 provides 8 pins (8-bit) adc voltage inputs. these input voltages should be positive and is limited at range of 0v to 2.048v. the minimum resolution (1-lsb) is 8mv. if the voltage is over this range, the divider resistor must be added and the divided voltage is also in the range of 0v to 2.048v. the maximum input voltage of the analog pin is 2.048v because the 8-bit adc has a 8mv lsb. really, the application of the pc monitoring would most often be conn ected to power suppliers. the voltage range of 0v to 2.048v can be connected to these analog inputs. the 3.3v and vsb5v should be reduced a factor with external resistors so as to obtain the input range.. there are 8 voltage inputs in the f71806 and the voltage divided formula is shown as follows: 2 1 2 12 r r r v vin v + = + for instance, where v +12v is the analog input voltage. if we choose r1=27k, r2=5.1k, the exact input vo ltage for v+12v will be 1.907v, which is within the tolerance. as for application circuit, it can be refer to the figure shown as follows.
july, 2007 v0.26p 17 f71806 r1 F71806F typical thermister connection 10k, 25 c r2 r vref 10k, 1% 2n3906 vin(lower than 2.048v) agnd(d-) d1/d2/d3 d1/d2/d3 c 2200pf 6.4.2 temperatur e monitoring the f71806 can be measured from 0c to 140c. the st atus depends on different situation. as connected to a bjt thermal diode, detected temperature ranges from 0c to 140c. as connected to a thermistor, detected temperature ranges from 0c to 127c. the temp erature format is as the following table: temperature ( high byte ) digital output 0c 0000 0000 1c 0000 0001 25c 0001 1001 50c 0011 0010 75c 0100 1011 90c 0101 1010 100c 0110 0100 140c 1000 1100 the f71806 can provide two external thermal sensors to detect temperature. when monitored temperature exceeds the over-tempera ture threshold value, ovt# (pin77) will be asserted until the te mperature goes below the hysteresis temperature.
july, 2007 v0.26p 18 f71806 t hyst to ovt# 6.4.3 fan speed count inputs are provided by the signals from fans equipped with tachometer outputs. the level of these signals should be set to ttl level, and maximum input voltage cannot be over vcc. if the input signals from the tachometer outputs are over the vcc, the external trimming circuit should be added to reduce the voltage to obtain the input specification. the normal circ uit and trimming circuits are shown as follows: fan out +12v gnd pull-up resister 4.7k ohms +12v fan input fanin 1 F71806F 22k~30k 10k fan connector fan out +12v gnd pull-up resister < 1k or totem-pole output +12v fan input F71806F > 1k fan with tach pull-up to +12v, or totem-pole putput and zener clamp 3.3v zener fan with tach pull-up to +12v, or totern-pole output and register attenuator fanin 1 fan out +5v gnd pull-up resister 4.7k ohms +5v fan input fanin1 F71806F 1k~2.7k 10k fan connector fan out +5v gnd pull-up resister < 1k or totem-pole output +5v fan input fanin1 F71806F > 1k fan with tach pull-up to +5v, or t o t e m-p o l e p u t pu t a n d z e n e r 3.3v zener fan with tach pull-up to +5v, or totern-pole output and register attenuator determine the fan counter according to:
july, 2007 v0.26p 19 f71806 rpm count 6 10 5 . 1 = in other words, the fan speed counter has been read from register, the fan speed can be evaluated by the following equation. as for fan, it would be best to use 2 pulses tachmeter output per round. count rpm 6 10 5 . 1 = 6.4.4 fan speed control the f71806 provides 2 fan speed control method s: 1. linear fan control 2. pwm duty cycle linear fan control the range of dc output is 0~3.3v, controlled by 8-bit register (cr6bh for fan1, cr7bh for fan2 and cr8bh for fan3). 1 lsb is about 0.013v. the output dc volt age is amplified by external op circuit, thus to reach maximum fan operation voltage, 12v. the output voltage will be given as followed: 255 value register bit - 8 programmed 3 . 3 (v) tage output_vol = and the suggested application circuit for linear fac control would be: dc output voltage r 3.9k r10k 12v pmos r27k 1 2 3 jp1 con3 r 10k d1 1n4148 r 4.7k c 47u fanin monitor c 0.1u 3 2 1 8 4 + - lm358 dc fan control with op pwm duty fan control the duty cycle of pwm can be programmed by a 8-bit register which are defined in the cr6bh, cr7bh and cr8bh. the default duty cycle is set to 100%, that is, the default 8-bit register s is set to ffh. the expression of duty can be represented as follows.
july, 2007 v0.26p 20 f71806 % 100 255 value register bit - 8 programmed (%) duty_cycle = +12v fan r1 r2 nmos pnp transistor c + - pwm clock input d s g +5v fan r1 r2 nmos pnp transistor c + - pwm clock input d s g 6.4.5 fan speed control mechanism there are 3 modes to control fan speed and they are manual, fan speed mode and temperature mode. for manual mode, it generally acts as pwm fan speed contro l. as for speed mode and temperature mode, they are more intelligent fan speed control and described as below: fan speed mode fan speed mode is an intelligent method according to expected fan speed pre-setting by bios. in the beginning, fan speed will be operated at full speed and the f71806 will get the full speed count value. after that, the fan speed will automatically rotate according to t he expected fan speed setting by bios. for instance, the register cr69h and cr6ah are used for this mode of fan1. temperature mode at this mode, f71806 provides the clever system to automatically control fan s peed related to temperature system. the f71806 can provide three temperature boundar ies and three intervals for user setting, and each interval has its related fan speed count. all these val ues should be set by bios first. in the f71806 design, the f71806 will auto-generate temperature boundaries (average value) between those boundaries that user setting, and it will auto-produce interval fan speed count (average value) between users setting value. if the temperature value is set to 40, 50 and 90 c, it will auto-generate two temperature boundaries value of 45 c ( this value is calculated automatically by har dware design of the f71806. (450+40)/2 =45 ) and 70 c. the same way, the related desired fan speed counts for each interval are 4200rpm, 3600rpm, 3000rpm, 2500rpm, 2000rpm and stop counts. when the temperature is within 50~70 c, the fan speed counts will be 3000rpm (registers cra4h~cra9h, crb4h~crb9h and crc4h~crc9h). the f71806 will auto-adjust pwmout (pwm_duty) to make fan speed match the expe cted value. it can be said that the fan will be turned on with a specific speed set by bios and automatically controlled with the temperature varying. the f71806 will
july, 2007 v0.26p 21 f71806 take charge of all the fan speed control and need no software support. default status sketch pwmout duty-cycle operating process in both ?fan speed? and ?temperature? modes, f71806 adjust pwmout ( pwm_duty1 (cr6b) of fan1, pwm_duty2 (cr7b) of f an2, pwm_duty3 (cr8b) of fan3 ) duty-cycle according to current fan count and expected fan count. it will operate as follows: (1). when expected count is ffffh, pwmout duty-cycle (pwm_duty)will be set to 00h to turn off fan. (2). when expected count is 0000h, pwmout duty-cycle (pwm_duty) will be set to ffh to turn on fan with full speed. (3). if both (1) and (2) are not true and keep_ stop (see index 60h) is set to 0: (a). when pwmout duty-cycle decrease to stop_duty( 00h), obviously the duty-cycle will decrease to 00h next, f71806 will keep duty-cycle at 00h 3 seconds 1 . after that, f71806 starts to compare current fan count and expect ed count in order to increase or decrease its duty-cycle. this ensures that if there is any glitch during the 3 seconds 1 period, f71806 will ignore it. (b). when pwmout duty-cycle increase from 00h to start_duty( 00h), f71806 also will keep duty-cycle at start_duty 3 seconds 1 . after that, f71806 starts to compare current fan count and expected count in order to increase or decrease it s duty-cycle. this ensure s that if there is any glitch during the 3 seconds 1 period, f71806 will ignore it. note 1: the period of hold_duty_time can be programmed at index 67h of fan1. desired counts (rpm) 4200 3600 3000 2500 2000 90 degree c 70 degree c 50 degree c 45 degree c 40 degree c stop counts auto-generated (average value) auto-generated (average value)
july, 2007 v0.26p 22 f71806 6.4.6 fan_fault# fan_fault will be asserted ( throuth pme# pin 73) when the fan speed doesn?t meet the expected fan speed within a programmable period (default is 3 seconds) when pwmout duty-cycle is 100%. fan_fault# expected fan count 3 sec ( default ) current fan count duty-cycle 100% 6.4.7 volt_fault# (voltage fault signal) when voltage leaps from the security range setting by bios, the warning signal volt_fault# will be activated. shown in figure. start stop start stop
july, 2007 v0.26p 23 f71806 volt_fault# high limit low limit 6.5 fdc the floppy disk controller provides the interface between a host processor and one floppy disk drives. it integrates a controller and a digital data separator with write pre-compensation, data rate selection logic, microprocessor interface, and a set of registers. the fdc supports data transfer rates of 250 kbps, 300 kbps, 500 kbps, and 1 mbps. it operates in pc/at mode and supports 3-mode type drives. the fdc configuration is handled by software and a se t of configuration registers. status, data, and control registers facilitate the inte rface between the ho st microprocessor and the disk drive, providing information about the condition and/or st ate of the fdc. these configuration registers can select the data rate, enable interrupts, drives, and dma modes, and indicate erro rs in the data or operati on of the fdc/fdd. the controller manages data transfers using a set of data transfer and control commands. these commands are handled in three phases: command, execution, and result. not all commands utilize all these three phases. 6.6 uart the f71806 provides two uart ports and supports irq sharing for system application. the uarts are used to convert data between parallel format and serial form at. they convert parallel data into serial format on transmission and serial format into parallel data on receiver side. the serial format is formed by one start bit, followed by five to eight data bits, a parity bit if programmed and one ( 1.5 or 2 ) stop bits. the uarts include complete modem control capability and an interrupt system that may be software trailed to the computing time required to handle the communication link. they have fi fo mode to reduce the number of interrupts presented to the host. both receiver and transmitter have a 16-byte fifo. 6.7 parallel port the parallel port in f71806 supports an ibm xt/at compatible parallel port ( spp ), bi-directional paralle
july, 2007 v0.26p 24 f71806 port ( bpp ), enhanced parallel port ( epp ), extended ca pabilities parallel port ( ecp ) mode. refer to the configuration registers for more inform ation on selecting the mode of operation. 7 register descriptions 7.1 global control registers the configuration register is used to control the behavior of the corr esponding devices. to configure the register, using the index port to se lect the index and then writing data port to alter the parameters. the default index port and data port are 0x4e and 0x4f respectively . pull down the sout1 pin to change the default value to 0x2e/0x2f (can be programmed by register!). to enable configuration, t he entry key 0x87 must be written to the index port. to disable configuration, write exit key 0x aa to the index port. following is a example to enable configuration and disable conf iguration by using debug. -o 4e 87 -o 4e 87 ( enable configuration ) -o 4e aa ( disable configuration )
july, 2007 v0.26p 25 f71806 7.1.1 software reset register ? index 02h bit name r/w default description 7-1 reserved - - reserved 0 soft_rst r/w 0 write 1 to reset the regi ster and device powered by vdd ( vcc ). 7.1.2 logic device number register ? index 07h bit name r/w default description 7-0 ldn r/w 00h 00h: select fdc dev ice configuration registers. 01h: select uart 1 device configuration registers. 02h: select uart 2 device configuration registers. 03h: select parallel port devic e configuration registers. 04h: select hardware monitor device configuration registers. 05h: reserved. 06h: select gpio device c onfiguration registers. 07h: select vid device c onfiguration registers. 0ah: select pme & acpi device configuration registers. 7.1.3 chip id register ? index 20h bit name r/w default description 7-0 chip_id1 r 03h chip id 1 of f71806. 7.1.4 chip id register ? index 21h bit name r/w default description 7-0 chip_id2 r 41h chip id2 of f71806. 7.1.5 vendor id register ? index 23h bit name r/w default description
july, 2007 v0.26p 26 f71806 7-0 vendor_id1 r 19h vendor id 1 of fintek devices. 7.1.6 vendor id register ? index 24h bit name r/w default description 7-0 vendor_id2 r 34h vendor id 2 of fintek devices. 7.1.7 software power down register ? index 25h bit name r/w default description 7-6 reserved - - reserved 5 reserved r/w 0 reserved. 4 softpd_hm r/w 0 power down the hardware monitor device. this will stop the hardware monitor clock. 3 softpd_prt r/w 0 power down the parallel port device. this will stop the parallel port clock. 2 softpd_ur2 r/w 0 power down the uart 2 device. this will stop the uart 2 clock. 1 softpd_ur1 r/w 0 power down the uart 1 device. this will stop the uart 1 clock. 0 softpd_fdc r/w 0 power down the fdc device. this will stop the fdc clock. 7.1.8 uart irq sharing register ? index 26h bit name r/w default description 7 clk24m_sel w 0 0: external clock is 48mhz 1: external clock is 24mhz 6-2 reserved - - reserved. 1 irq_mode r/w 0 0: pci irq sharing mode (low level). 1: isa irq sharing mode (low pulse). o irq_shar r/w 0 0: disable irq sharing of two uart devices. 1: enable irq sharing of two uart devices.
july, 2007 v0.26p 27 f71806 7.1.9 port select register ? index 27h bit name r/w default description 7-5 reserved - - reserved. 4 port_4e_en w - the default value of the register is power on trap by sout1. pull down to select configuration register port 2e/2f, else 4e/4f. the port could be changed by writing this register. 0: configuration register port is 2e/2f. 1: configuration register port is 4e/4f. 3-0 reserved - - reserved. 7.1.10 power led function select register ? index 28h bit name r/w default description 7 reserved - - reserved. 6-5 vddled_sel r/w 2 ?| b11 vddled function select, powered by vdd. 00: vddled always output low. 01: vddled tri-state 10: vddled output 0.5hz clock. 11: vddled output 1hz clock. ( clock output is inverse with vsbled clock output ) (powered by vdd) 4 vddled_en r/w 0 vddled enable, powered by vdd. 0: the function of pcirst5#/gp 15/vddled is pcirst5#/gp15. 1: the function of pcirst 5#/gp15/vddled is vddled. (powered by vdd) 3 reserved - - reserved.
july, 2007 v0.26p 28 f71806 2-1 vsbled_sel r/w 2 ?| b11 vsbled function select, powered by vsb3v. 00: vsbled always output low. 01: vsbled tri-state 10: vsbled output 0.5hz clock. 11: vsbled output 1hz clock. (powered by vsb) 0 vsbled_en r/w 0 vsbled enable, powered by vsb3v. 0: the function of pwrok2/g p25/vsbled is pwrok2/gp25. 1: the function of pwrok2/gp25/vsbled is vsbled. (powered by vsb) 7.1.11 multi function select 1 register ? index 29h (powered by vdd) bit name r/w default description 7 rst_drv_dis r 1 0: enable pcirstx pin driving. 1: disable pcirstx pin driving. power on trap by dtr2# 6-5 reserved - - reserved. 4 pin29_irrx_en w 0 0: the function of pin 29 is gpio3/voltage_fault1. 1: the function of pin 29 is irrx. 3 beep_gpen r/w 0 0: the function of gpio4/voltage_fau lt2#/beep is gpio4/voltage_fault2#. 1: the function of gpio4/v oltage_fault2#/beep is beep. 2 fanctl1_gpen r/w 0 0: the function of gpio5/voltage_fault 3#/fanctl1 is pio5/voltage_fault3#. 1: the function of gpio5/volt age_fault3#/fanctl1 is fanctl1. 1 vin8_en r/w 0 0: the function of pcirstin#/vin8 is pcirstin#. 1: the function of pcirstin#/vin8 is vin8. 0 vin4_en r/w 0 0: the function of atxpg/vin4 is atxpg. 1: the function of atxpg/vin4 is vin4.
july, 2007 v0.26p 29 f71806 7.1.12 multi function select 2 register ? index 2ah (powered by vdd) bit name r/w default description 7 reserved - - reserved. 6 gpio16_en r/w 0 0: the function of irtx/gpio16 is irtx. 1: the function of irtx/gpio16 is gpio16. 5 gpio15_en r/w 0 it works when vddled_en is 0. 0: the function of pcirst5#/gpio15 is pcirst5#. 1: the function of pc irst5#/gpio15 is gpio15. 4 gpio14_en r/w 0 0: the function of pcirst3#/gpio14 is pcirst3#. 1: the function of pc irst3#/gpio14 is gpio14. 3 gpio13_en r/w 0 0: the function of pcirst2#/gpio13 is pcirst2#. 1: the function of pc irst2#/gpio13 is gpio13. 2 gpio12_en r/w 0 0: the function of pwro k1/gpio12 is pwrok1. 1: the function of pw rok1/gpio12 is gpio12. 1 gpio11_en r/w 0 0: the function of pcirst1#/gpio11 is pcirst1#. 1: the function of pc irst1#/gpio11 is gpio11. 0 gpio10_en r/w 0 0: the function of rstcon#/gpio10 is rstcon#. 1: the function of pc irst0#/gpio10 is gpio10. 7.1.13 multi function select 3 register ? index 2bh (powered by vdd) bit name r/w default description 7-6 gpio6_sel r/w 00 00: the function of gpio6/voltage_f ault4#/wdtrst1#/ovt# is gpio6. 01: the function of gpio6/vol tage_fault4#/wdtrst1#/ovt# is voltage_fault4#. 10: the function of gpio6/voltage_fau lt4#/wdtrst1#/ovt# is wdtrst1#. 11: the function of gpio6/voltage_f ault4#/wdtrst1# /ovt# is ovt#. ( powered by vdd, reset by vdd3vok ) 5 vin3f_en r/w 0 functions when fanctl1_gpen is 0. 0: the function of gpio5/voltage_fault3# is gpio5. 1: the function of gpio5/volt age_fault3# is voltage_fault3#.
july, 2007 v0.26p 30 f71806 4 vin2f_en r/w 0 functions when beep_gpen is 0. 0: the function of gpio4/voltage_fault2# is gpio4. 1: the function of gpio4/volt age_fault2# is voltage_fault2#. 3 vin1f_en r/w 0 0: the function of gpio3/voltage_fault1# is gpio3. 1: the function of gpio3/volt age_fault1# is voltage_fault1#. 2 vin7_id2_en r/w 0 0: the function of gpio2 pin is gpio2. 1: reserved. 1 vin7_id1_en r/w 0 0: the function of gpio1 pin is gpio1. 1: reserved. 0 vin7_id0_en r/w 0 0: the function of gpio0 pin is gpio0. 1: reserved. 7.1.14 multi function select 4 register ? index 2ch (powered by vsb3v) bit name r/w default description 7 gpio27_en r/w 0 0: the function of rsmrst#/gpio27 is rsmrst#. 1: the function of rs mrst#/gpio27 is gpio27. 6 gpio26_en r/w 0 0: the function of pcirst4#/gpio26 is pcirst4#. 1: the function of pc irst4#/gpio26 is gpio26. 5 gpio25_en r/w 0 functions when vsbled_en is 0. 0: the function of pwro k2/gpio25 is pwrok2. 1: the function of pw rok2/gpio25 is gpio25. 4 reserved - - reserved. 3 gpio23_en r/w 0 0: the function of pson#/gpio23 is pson#. 1: the function of pson#/gpio23 is gpio23. 2 gpio22_en r/w 0 0: the function of pwswin#/gpio22 is pwswin#. 1: the function of pw swin#/gpio22 is gpio22. 1 gpio21_en r/w 0 0: the function of pme#/gpio21 is pme#. 1: the function of pme#/gpio21 is gpio21.
july, 2007 v0.26p 31 f71806 0 gpio20_en r/w 0 0: the function of pwswout#/gpio20 is pwswout#. 1: the function of pwswout#/gpio20 is gpio20. 7.1.15 multi function select 5 register ? index 2dh (powered by vsb3v) bit name r/w default description 7 clk24m_sel r 0 0: external clock is 48mhz 1: external clock is 24mhz. 6 pin29_irrx_en r 0 0: the function of pin 29 is gpio3/voltage_fault1. 1: the function of pin 29 is irrx. 5 pin77_drv_en r/w 0 set the output type of pin 77 when programmed as gpio24. 0: open drain. 1: push-pull. 4 pin70_drv_en r/w 0 set the output type of pin 70 when programmed as gpio30. 0: open drain. 1: push-pull. 3-2 gpio24_sel r/w 01 00: the function of ovt# /gpio24/wdtrst2# is gpio24. 01: the function of ovt# /gpio24/wdtrst2# is ovt#. 10: the function of ovt# /gpio24/wdtrst2# is wdtrst2#. 11: reserved. 1 gpio31_en r/w 0 0: the function of s3#/gpio31 is s3#. 1: the function of s3#/gpio31 is gpio31. 0 gpio30_en r/w 0 0: the function of irrx/gpio30 is irrx. 1: the function of irrx/gpio30 is gpio30.
july, 2007 v0.26p 32 f71806 7.2 fdc registers 7.2.1 logic device number register logic device number register ? index 07h bit name r/w default description 7-0 ldn r/w 00h 00h: select fdc dev ice configuration registers. 01h: select uart 1 device configuration registers. 02h: select uart 2 device configuration registers. 03h: select parallel port devic e configuration registers. 04h: select hardware monitor device configuration registers. 05h: reserved. 06h: select gpio device c onfiguration registers. 07h: select vid device c onfiguration registers. 0ah: select pme & acpi device configuration registers. 7.2.2 fdc configuration registers fdc device enable register ? index 30h bit name r/w default description 7-1 reserved - - reserved 0 fdc_en r/w 1 0: disable fdc. 1: enable fdc. base address high register ? index 60h bit name r/w default description 7-0 base_addr_hi r/w 03h the msb of fdc base address. base address low register ? index 61h bit name r/w default description 7-0 base_addr_lo r/w f0h the lsb of fdc base address.
july, 2007 v0.26p 33 f71806 irq channel select register ? index 70h bit name r/w default description 7-4 reserved - - reserved. 3-0 selfdcirq r/w 06h select the irq channel for fdc. dma channel select register ? index 74h bit name r/w default description 7-3 reserved - - reserved. 2-0 selfdcdma r/w 010 select the dma channel for fdc. fdd mode register ? index f0h bit name r/w default description 7-4 reserved - - reserved. 3-2 if_mode r/w 11 00: model 30 mode. 01: ps/2 mode. 10: reserved. 11: at mode (default). 1 fdmamode r/w 1 0: enable burst mode. 1: non-busrt mode (default). 0 en3mode r/w 0 0: normal floppy mode (default). 1: enhanced 3-mode fdd. fdd drive type register ? index f2h bit name r/w default description 7-2 reserved - - reserved. 1-0 fdd_type r/w 11 fdd drive type. fdd selection register ? index f4h bit name r/w default description 7-5 reserved - - reserved.
july, 2007 v0.26p 34 f71806 4-3 fdd_drt r/w 00 data rate table select, refer to table a. 00: select regular drives and 2.88 format. 01: 3-mode drive. 10: 2 mega tape. 11: reserved. 2 reserved - - reserved. 1-0 fdd_dt r/w 00 drive type select, refer to table b. table a data rate table select data ra te selected data rate densel fdd_drt[1] fdd_drt[0] datarate1 datarate0 mfm fm 0 0 500k 250k 1 0 1 300k 150k 0 1 0 250k 125k 0 0 0 1 1 1meg --- 1 0 0 500k 250k 1 0 1 500k 250k 0 1 0 250k 125k 0 0 1 1 1 1meg --- 1 0 0 500k 250k 1 0 1 2meg --- 0 1 0 250k 125k 0 1 0 1 1 1meg --- 1 table b drive type fdd_dt1 fdd_dt0 drvden0 remark 0 0 densel 4/2/1 mb 3.5? 2/1 mb 5.25? 1/1.6/1 mb 3.5? (3-mode ) 0 1 datarate1 1 0 densel# 1 1 datarate0
july, 2007 v0.26p 35 f71806 7.2.3 device registers 7.2.3.1 status register a (ps/2 mode) ? base + 0 bit name r/w default description 7 intpend r 0 this bit indicates the state of the interrupt output. 6 drv2_n r - 0: a second drive has been installed. 1: a second drive has not been installed. 5 step r 0 this bit indicates the complement of step# disk interface output. 4 trk0_n r - this bit indicates the state of trk0# disk interface input. 3 hdsel r 0 this bit indicates the complement of hdsel# disk interface output. 0: side 0. 1: side 1. 2 index_n r - this bit indicates the state of index# disk interface input. 1 wpt_n r - this bit indicates the state of wpt# disk interface input. 0: disk is write-protected. 1: disk is not write-protected. 0 dir r 0 this bit indicates the comp lement of dir# disk interface output. 7.2.3.2 status regist er a (model 30 mode) ? base + 0 bit name r/w default description 7 intpend r 0 this bit indicates the state of the interrupt output. 6 drq r 0 this bit indicates the state of the drq signal. 5 step_ff r 0 this bit indicates the complement of latched step# disk interface output. 4 trk0 r - this bit indicates the complement of trk0# disk interface input. 3 hdsel_n r 1 this bit indicates the state of hdsel# disk interface output. 0: side 0. 1: side 1. 2 index r - this bit indicates the comp lement of index# disk interface input. 1 wpt r - this bit indicates the complement of wpt# disk interface input. 0: disk is write-protected. 1: disk is not write-protected. 0 dir_n r 1 this bit indicates the state of dir# disk interface output. 0: head moves in inward direction. 1: head moves in outward direction. 7.2.3.3 status register b (ps/2 mode) ? base + 1 bit name r/w default description 7-6 reserved r 11 reserved. return 11b when read. 5 dr0 r 0 drive select 0. this bit reflec ts the bit 0 of digital output register. 4 wdata r 0 this bit changes state at every rising edge of wdata#. 3 rdata r 0 this bit changes state at every rising edge of rdata#.
july, 2007 v0.26p 36 f71806 2 wgate r 0 this bit indicates the complement of wgate# disk interface output. 1 moten1 r 0 this bit indicates the complement of mob# disk interface output. not support in this design. 0 moten0 r 0 this bit indicates the comp lement of moa# disk interface output. 7.2.3.4 status regist er b (model 30 mode) ? base + 1 bit name r/w default description 7 drv2_n r - 0: a second drive has been installed. 1: a second drive has not been installed. 6 dsb_n r 1 this bit indicates the state of dr vb# disk interface output. not support in this design. 5 dsa_n r 1 this bit indicates the state of drva# disk interface output. 4 wdata_ff r 0 this bit is latched at the rising edge of wdata# and is cleared by a read from the digital input register. 3 rdata_ff r 0 this bit is latched at the rising edge of rdata# and is cleared by a read form the digital input register. 2 wgate_ff r 0 this bit is latched at the falling edge of wgate# and is cleared by a read from the digital input register. 1 dsd_n r 1 this bit indicates the complem ent of drvd# disk interface output. not support in this design. 0 dsc_n r 1 this bit indicates the complem ent of drvc# disk interface output. not support in this design. 7.2.3.5 digital output register ? base + 2 bit name r/w default description 7 moten3 r 0 motor enable 3. not support in this design. 6 moten2 r 0 motor enable 2. not support in this design. 5 moten1 r/w 0 motor enable 1. used to control mob#. mob# is not sup port in this design. 4 moten0 r/w 0 motor enable 0. used to control moa#. 3 damen r/w 0 dma enable. this bit has two mode of operation. pc-at and model 30 mode: write 1 will enable dma and irq, write 0 will disable dma and irq. ps/2 mode: this bit is reserved. dma and irq are always enabled in ps/2 mode. 2 reset r 0 write 0 to this bit will reset the controller. i will remain in reset condition until a 1 is written. 1 dsd_n r 1 this bit indicates the complem ent of drvd# disk interface output. not support in this design. 0 dsc_n r 1 this bit indicates the complem ent of drvc# disk interface output. not support in this design.
july, 2007 v0.26p 37 f71806 7.2.3.6 tape drive register ? base + 3 bit name r/w default description 7-6 reserved r 00 reserved. return 00b when read. 5-4 typeid r 11 reserved in normal function, return 11b when read. if 3 mode fdd function is enabled. these bits indicate the drive type id. 3-2 reserved r 11 reserved. return 11b when read in normal function. return 00b when read in 3 mode fdd function. 1-0 tapesel r/w 0 these bits assign a logical drive number to be a tape drive. 7.2.3.7 main status register ? base + 4 bit name r/w default description 7 rqm r 0 request for master indicates that t he controller is ready to send or receive data from the up through the fifo. 6 dio r 0 data i/o (direction): 0: the controller is expecting a byte to be written to the data register. 1: the controller is expecting a byte to be read from the data register. 5 non_dma r 0 non dma mode: 0: the controller is in dam mode. 1: the controller is interrupt or software polling mode. 4 fdc_busy r 0 this bit indicate that a read or write command is in process. 3 drv3_busy r 0 fdd number 3 is in seek or calibration condition. fdd number 3 is not support in this design. 2 drv2_busy r 0 fdd number 2 is in seek or calibration condition. fdd number 2 is not support in this design. 1 drv1_busy r 0 fdd number 1 is in seek or calibration condition. fdd number 1 is not support in this design. 0 drv0_busy r 0 fdd number 0 is in seek or calibration condition. 7.2.3.8 data rate select register ? base + 4 bit name r/w default description 7 softrst w 0 a 1 written to this bit will softwa re reset the controller. auto clear after reset. 6 pwrdown w 0 a 1 to this bit will put the controller into low power mode which will turn off the oscillator and data separator circuits. 5 reserved - - return 0 when read.
july, 2007 v0.26p 38 f71806 4-2 precomp w 000 select the valu e of write precompensation: 250k-1mbps 2mbps 000: default delays default delays 001: 41.67ns 20.8ns 010: 83.34ns 41.17ns 011: 125.00ns 62.5ns 100: 166.67ns 83.3ns 101: 208.33ns 104.2ns 110: 250.00ns 125.00ns 111: 0.00ns (disabled) 0.00ns (disabled) the default value of corresponding data rate: 250kbps: 125ns 300kbps: 125ns 500kbps: 125ns 1mbps: 41.67ns 2mbps: 20.8ns 1-0 drate w 10 data rate select: mfm fm 00: 500kbps 250kbps 01: 300kbps 150kbps 10: 250kbps 125kbps 11: 1mbps illegal 7.2.3.9 data (fifo) register ? base + 5 bit name r/w default description 7-0 data r/w 00h the fifo is used to transfer all commands, data and status between controller and the system. the data register consists of four status registers in a stack with only one register presented to the data bus at a time. the fifo is default disabled and could be enabled via the configure command. status registers 0 bit name r/w default description 7-6 ic r - interrupt code : 00: normal termination of command. 01: abnormal termination of command. 10: invalid command. 11: abnormal termination caused by poling. 5 se r - seek end. set when a seek or recalibrate or a read or write with implied seek command is completed. 4 ec r - equipment check. 0: no error 1: when a fault signal is received form the fdd or the trk0# signal fails to occur after 77 step pulses.
july, 2007 v0.26p 39 f71806 3 nr r - not ready. 0: drive is ready 1: drive is not ready. 2 hd r - head address. the current head address. 1-0 ds r - drive select. 00: drive a selected. 01: drive b selected. 10: drive c selected. 11: drive d selected. status registers 1 bit name r/w default description 7 en r - end of track. set when the fdc tries to access a sector beyond the final sector of a cylinder. 6 de r - data error. the fdc detect a crc error in either the id field or the data field of a sector. 4 or r - overrun/underrun. set when the fdc is not serviced by the host system within a certain time interval during data transfer. 3 reserved - - unused. this bit is always ?0? 2 nd r - no data. set when the following conditions occurred: 1. the specified sector is not found during any read command. 2. the id field cannot be read without errors during a read id command. 3. the proper sector sequence cann ot be found during a read track command. 1 nw r - no writable set when wpt# is active during execution of write commands. 0 ma r - missing address mark. set when the following conditions occurred: 1. cannot detect an id address mark at the specified track after encountering the index pulse form the index# pin twice. 2. cannot detect a data address mark or a deleted data address mark on the specified track. status registers 2 bit name r/w default description 7 reserved - - unused. this bit is always ?0?. 6 cm r - control mark. set when following conditions occurred: 1. encounters a deleted data address mark during a read data command. 2. encounters a data address mark during a read deleted data command.
july, 2007 v0.26p 40 f71806 5 dd r - data error in data field. the fdc detects a crc error in the data field. 4 wc r - wrong cylinder. set when the track address from the sector id field is different from the track address maintained inside the fdc. 3 se r - scan equal. set if the equal condition is satisfied during execution of the scan command. 2 sn r - scan not satisfied. set when the fdc cannot find a sector on the track which meets the desired condition during any scan command. 1 bc r - bad cylinder. the track address from the sector id fi eld is different from the track address maintained inside the fdc and is equal to ffh which indicates a bad track. 0 md r - missing data address mark. set when the fdc cannot detect a data address mark or a deleted data address mark. status registers 3 bit name r/w default description 7 reserved - - unused. this bit is always ?0?. 6 wp r - write protect. indicates the status of wpt# pin. 5 reserved r - unused. this bit is always ?1?. 4 t0 r - track 0. indicates the status of the trk0# pin. 3 reserved. r - unused. this bit is always ?1?. 2 hd r - head address. indicates the status of the hdsel# pin. 1 ds1 r - 0 ds0 r - drive select. these two bits indicate the ds1, ds0 bits in the command phase. 7.2.3.10 digital input re gister (pc-at mode) ? base + 7 bit name r/w default description 7 dskchg r - this bit indicates the complement of dskchg# disk interface input. 6-0 reserved r - reserved. 7.2.3.11 digital input register (ps/2 mode) ? base + 7 bit name r/w default description 7 dskchg r - this bit indicates the complement of dskchg# disk interface input. 6-3 reserved - - reserved.
july, 2007 v0.26p 41 f71806 2-1 drate r 10 these bits indicate the status of the drate programmed through the data rate select register or co nfiguration control register. 0 highden_n r 1 0: 1mbps or 500kbps data rate is chosen. 1: 300kbps or 250kbps data rate is chosen. 7.2.3.12 digital input re gister (model 30 mode) ? base + 7 bit name r/w default description 7 dskchg_n r - this bit indicates the state of dskchg# disk interface input. 6-4 reserved - - reserved. 3 dmaen r 0 this bit reflects the dma bit in digital output register. 2 nopre r 0 this bit reflects the nopre bit in configuration control register. 1-0 drate r 10 these bits indicate the status of drate programmed through the data rate select register or config uration control register. 7.2.3.13 configuration control re gister (pc-at and ps/2 mode) ? base + 7 bit name r/w default description 7-2 reserved - - reserved. 1-0 drate w 10 these bit determine the data rate of the floppy controller. see drate bits in data rate select register. 7.2.3.14 configuration contro l register (model 30 mode) ? base + 7 bit name r/w default description 7-3 reserved - - reserved. 2 nopre w 0 this bit could be programmed thr ough configuration control register and be read through the bit 2 in digital input r egister in model 30 mode. but it has no functionality. 1-0 drate w 10 these bit determine the data rate of the floppy controller. see drate bits in data rate select register. 7.2.3.15 fdc commands terminology: c cylinder number 0 -256 d data pattern dir step direction 0: step out 1: step in ds0 drive select 0 ds1 drive select 1 dtl data length
july, 2007 v0.26p 42 f71806 ec enable count eot end of track efifo enable fifo 0: fifo is enabled. 1: fifo is disabled. eis enable implied seek fifothr fifo threshold gap alters gap length gpl gap length h/hds head address hlt head load time hut head unload time lock lock efifo, fifothr, ptrtrk bits. prevent these bits from being affected by software reset. mfm mfm or fm mode 0: fm 1: mfm mt multi-track n sector size code. all values up to 07h are allowable. 00: 128 bytes 01: 256 bytes .. .. 07 16 kbytes ncn new cylinder number nd non-dma mode ow overwritten pcn present cylinder number poll polling disable 0: polling is enabled. 1: polling is disabled. pretrk precompensation start track number r sector address rcn relative cylinder number sc sector per cylinder sk skip deleted data address mark srt step rate time st0 status register 0 st1 status register 1 st2 status register 2 st3 status register 3 wgate write gate alters timing of we. read data phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remark command w mt mfm sk 0 0 1 1 0 command code w 0 0 0 0 0 hds ds1 ds0 w ----------------------------- c --------------------------- w ----------------------------- h --------------------------- w ----------------------------- r --------------------------- sector id information prior to command execution
july, 2007 v0.26p 43 f71806 w ------------------------------ n --------------------------- w ---------------------------- eot -------------------------- w ---------------------------- gpl -------------------------- w ---------------------------- dtl -------------------------- execution data transfer between the fdd and system result r ---------------------------- st0 -------------------------- r ----------------------------- st1 -------------------------- r ---------------------------- st2 -------------------------- status information after command execution. r ----------------------------- c --------------------------- r ----------------------------- h --------------------------- r ----------------------------- r --------------------------- r ----------------------------- n --------------------------- sector id information after command execution. read deleted data phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remark command w mt mfm sk 0 1 1 0 0 command code w 0 0 0 0 0 hds ds1 ds0 w ----------------------------- c --------------------------- w ----------------------------- h --------------------------- w ----------------------------- r --------------------------- w ------------------------------ n --------------------------- w ---------------------------- eot -------------------------- w ---------------------------- gpl -------------------------- w ---------------------------- dtl -------------------------- sector id information prior to command execution execution data transfer between the fdd and system result r ---------------------------- st0 -------------------------- r ----------------------------- st1 -------------------------- r ---------------------------- st2 -------------------------- status information after command execution. r ----------------------------- c --------------------------- r ----------------------------- h --------------------------- r ----------------------------- r --------------------------- r ----------------------------- n --------------------------- sector id information after command execution.
july, 2007 v0.26p 44 f71806 read a track phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remark command w 0 mfm 0 0 0 0 1 0 command code w 0 0 0 0 0 hds ds1 ds0 w ----------------------------- c --------------------------- w ----------------------------- h --------------------------- w ----------------------------- r --------------------------- w ------------------------------ n --------------------------- w ---------------------------- eot -------------------------- w ---------------------------- gpl -------------------------- w ---------------------------- dtl -------------------------- sector id information prior to command execution execution data transfer between the fdd and system. fdd reads contents of all cylinders from index hole to eot. result r ---------------------------- st0 -------------------------- r ----------------------------- st1 -------------------------- r ---------------------------- st2 -------------------------- status information after command execution. r ----------------------------- c --------------------------- r ----------------------------- h --------------------------- r ----------------------------- r --------------------------- r ----------------------------- n --------------------------- sector id information after command execution. read id phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remark command w 0 mfm 0 0 1 0 1 0 command code w 0 0 0 0 0 hds ds1 ds0 execution the first correct id information on the cylinder is stored in data register. result r ---------------------------- st0 -------------------------- r ----------------------------- st1 -------------------------- r ---------------------------- st2 -------------------------- status information after command execution.
july, 2007 v0.26p 45 f71806 r ----------------------------- c --------------------------- r ----------------------------- h --------------------------- r ----------------------------- r --------------------------- r ----------------------------- n --------------------------- disk status after the command has been completed. verify phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remark command w mt mfm sk 1 0 1 1 0 command code w ec 0 0 0 0 hds ds1 ds0 w ----------------------------- c --------------------------- w ----------------------------- h --------------------------- w ----------------------------- r --------------------------- w ------------------------------ n --------------------------- w ---------------------------- eot -------------------------- w ---------------------------- gpl -------------------------- w -------------------------- dtl/sc ------------------------ sector id information prior to command execution execution no data transfer result r ---------------------------- st0 -------------------------- r ----------------------------- st1 -------------------------- r ---------------------------- st2 -------------------------- status information after command execution. r ----------------------------- c --------------------------- r ----------------------------- h --------------------------- r ----------------------------- r --------------------------- r ----------------------------- n --------------------------- sector id information after command execution. version phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remark command w 0 0 0 1 0 0 0 0 command code result r 1 0 0 1 0 0 0 0 enhanced controller write data phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remark
july, 2007 v0.26p 46 f71806 command w mt mfm 0 0 0 1 0 1 command code w 0 0 0 0 0 hds ds1 ds0 w ----------------------------- c --------------------------- w ----------------------------- h --------------------------- w ----------------------------- r --------------------------- w ------------------------------ n --------------------------- w ---------------------------- eot -------------------------- w ---------------------------- gpl -------------------------- w ---------------------------- dtl -------------------------- sector id information prior to command execution execution data transfer between the fdd and system. result r ---------------------------- st0 -------------------------- r ----------------------------- st1 -------------------------- r ---------------------------- st2 -------------------------- status information after command execution. r ----------------------------- c --------------------------- r ----------------------------- h --------------------------- r ----------------------------- r --------------------------- r ----------------------------- n --------------------------- sector id information after command execution. write deleted data phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remark command w mt mfm 0 0 1 0 0 1 command code w 0 0 0 0 0 hds ds1 ds0 w ----------------------------- c --------------------------- w ----------------------------- h --------------------------- w ----------------------------- r --------------------------- w ------------------------------ n --------------------------- w ---------------------------- eot -------------------------- w ---------------------------- gpl -------------------------- w ---------------------------- dtl -------------------------- sector id information prior to command execution execution data transfer between the fdd and system. result r ---------------------------- st0 -------------------------- r ----------------------------- st1 -------------------------- status information after command
july, 2007 v0.26p 47 f71806 r ---------------------------- st2 -------------------------- execution. r ----------------------------- c --------------------------- r ----------------------------- h --------------------------- r ----------------------------- r --------------------------- r ----------------------------- n --------------------------- sector id information after command execution. format a track phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remark command w 0 mfm 0 0 1 1 0 1 command code w 0 0 0 0 0 hds ds1 ds0 w ------------------------------ n --------------------------- bytes/sector w ---------------------------- sc -------------------------- sectors/cylinder w ---------------------------- gpl -------------------------- gap 3 length w ----------------------------- d --------------------------- data pattern ------------------------------ c --------------------------- w ------------------------------ h --------------------------- w ------------------------------ r --------------------------- execution for each sector ( repeat ) w ----------------------------- n -------------------------- input sector parameter. result r ---------------------------- st0 -------------------------- r ----------------------------- st1 -------------------------- r ---------------------------- st2 -------------------------- status information after command execution. r ------------------------- undefined ---------------------- r ------------------------- undefined ---------------------- r -------------------------- undefined ----------------------- r ------------------------- undefined ---------------------- recalibrate phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remark command w 0 0 0 0 0 1 1 1 command code w 0 0 0 0 0 0 ds1 ds0 execution head retracted to track 0
july, 2007 v0.26p 48 f71806 sense interrupt status phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remark command w 0 0 0 0 1 0 0 0 command code result r ---------------------------- st0 -------------------------- r ---------------------------- pcn -------------------------- specify phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remark command w 0 0 0 0 0 0 1 1 command code w |------------------ srt -------------------| |------------------ hut -------------------| w |------------------------------------- srt ---------------------------------------| nd seek phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remark command w 0 0 0 0 1 1 1 1 command code w 0 0 0 0 0 hds ds1 ds0 w ---------------------------- ncn -------------------------- execution head positioned over proper cylinder on diskette configure phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remark command w 0 0 0 1 0 0 1 1 command code w 0 0 0 0 0 hds ds1 ds0 w 0 eis efifo poll |---------------- fifothr ---------------| w ---------------------------- pretrk -------------------------- execution internal registers written relative seek phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remark command w 1 dir 0 0 1 1 1 1 command code w 0 0 0 0 0 hds ds1 ds0
july, 2007 v0.26p 49 f71806 w ---------------------------- rcn -------------------------- perpendicular mode phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remark command w 0 0 0 1 0 0 1 0 command code w ow 0 d3 d2 d1 d0 gap wgate lock phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remark command w lock 0 0 1 0 1 0 0 command code result r 0 0 0 lock 0 0 0 0 dumpreg phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remark command w 0 0 0 0 1 1 1 0 command code result r -------------------------- pcn ( drive 0 ) ------------------------ r -------------------------- pcn ( drive 0 ) ------------------------ r -------------------------- pcn ( drive 0 ) ------------------------ r -------------------------- pcn ( drive 0 ) ------------------------ r |------------------ srt -------------------| |------------------ hut -------------------| r |------------------------------------- srt ---------------------------------------| nd r -------------------------- sc/eot ------------------------ r lock 0 d3 d2 d1 d0 gap wgate r 0 eis efifo poll |---------------- fifothr ---------------| r ---------------------------- pretrk -------------------------- sense drive status phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remark command w 0 0 0 0 0 1 0 0 command code w 0 0 0 0 0 hds ds1 ds0 result r ---------------------------- st3 -------------------------- status information abut disk drive
july, 2007 v0.26p 50 f71806 invalid phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remark command w ---------------------------- in valid codes -------------------------- fdc goes to standby state. result r ---------------------------- st0 -------------------------- st0 = 80h 7.3 uart1 registers 7.3.1 logic device number register logic device number register ? index 07h bit name r/w default description 7-0 ldn r/w 00h 00h: select fdc dev ice configuration registers. 01h: select uart 1 device configuration registers. 02h: select uart 2 device configuration registers. 03h: select parallel port devic e configuration registers. 04h: select hardware monitor device configuration registers. 05h: reserved. 06h: select gpio device c onfiguration registers. 07h: select vid device c onfiguration registers. 0ah: select pme & acpi device configuration registers. 7.3.2 uart 1 confi guration registers uart 1 device enable register ? index 30h bit name r/w default description 7-1 reserved - - reserved 0 ur1_en r/w 1 0: disable uart 1. 1: enable uart 1.
july, 2007 v0.26p 51 f71806 base address high register ? index 60h bit name r/w default description 7-0 base_addr_hi r/w 03h the msb of uart 1 base address. base address low register ? index 61h bit name r/w default description 7-0 base_addr_lo r/w f8h the lsb of uart 1 base address. irq channel select register ? index 70h bit name r/w default description 7-4 reserved - - reserved. 3-0 selur1irq r/w 4h select t he irq channel for uart 1. rs485 enable register ? index f0h bit name r/w default description 7-5 reserved - - reserved. 4 rs485_en r/w 0 0: rs232 driver. 1: rs485 driver. auto drive rts# low when transmitting data. 3-0 reserved - - reserved. 7.3.3 device registers 7.3.3.1 receiver buffer register ? base + 0 bit name r/w default description 7-0 rbr r 00h the data received. read only when lcr[7] is 0 7.3.3.2 transmitter holding register ? base + 0 bit name r/w default description 7-0 thr w 00h data to be transmitted. write only when lcr[7] is 0
july, 2007 v0.26p 52 f71806 7.3.3.3 divisor latch (lsb) ? base + 0 bit name r/w default description 7-0 dll r/w 01h baud generator divisor low byte. access only when lcr[7] is 1. 7.3.3.4 divisor latch (msb) ? base + 1 bit name r/w default description 7-0 dlm r/w 00h baud generator divisor high byte. access only when lcr[7] is 1. 7.3.3.5 interrupt enable register ? base + 1 bit name r/w default description 7-4 reserved - - reserved. 3 edssi r/w 0 enable modem status interrupt. access only when lcr[7] is 0. 2 elsi r/w 0 enable line status error in terrupt. access only when lcr[7] is 0. 1 etbfi r/w 0 enable transmitter holding register empty interrupt. access only when lcr[7] is 0. 0 erbfi r/w 0 enable received data available interrupt. access only when lcr[7] is 0. 7.3.3.6 interrupt iden tification register ? base + 2 bit name r/w default description 7 fifo_en r 0 0: fifo is disabled 1: fifo is enabled. 6 fifo_en r 0 0: fifo is disabled 1: fifo is enabled. 5-4 reserved - - reserved. 3-1 irq_id r 000 000: interrupt is caused by modem status 001: interrupt is caused by transmitter holding register empty 010: interrupt is caused by received data available. 110: interrupt is caused by character timeout 011: interrupt is caused by line status. 0 irq_pendn r 1 1: interrupt is not pending. 0: interrupt is pending. 7.3.3.7 fifo control register ? base + 2 bit name r/w default description 7-6 rcv_trig w 00 00: receiver fifo trigger level is 1. 01: receiver fifo trigger level is 4. 10: receiver fifo trigger level is 8. 11: receiver fifo trigger level is 14. 5-3 reserved - - reserved. 2 clrtx r 0 reset the transmitter fifo. 1 clrrx r 0 reset the receiver fifo.
july, 2007 v0.26p 53 f71806 0 fifo_en r 0 0: disable fifo. 1: enable fifo. 7.3.3.8 line control register ? base + 3 bit name r/w default description 7 dlab r/w 0 0: divisor latch can?t be accessed. 1: divisor latch can be accessed via base and base+1. 6 setbrk r/w 0 0: transmitter is in normal condition. 1: transmit a break condition. 5 stkpar r/w 0 4 eps r/w 0 3 pen r/w 0 xx0: parity bit is disable 001: parity bit is odd. 011: parity bit is even 101: parity bit is logic 1 111: parity bit is logic 0 2 stb r/w 0 0: stop bit is one bit 1: when word length is 5 bit stop bit is 1.5 bit else stop bit is 2 bit 1-0 wls r/w 00 00: word length is 5 bit 01: word length is 6 bit 10: word length is 7 bit 11: word length is 8 bit 7.3.3.9 modem control register ? base + 4 bit name r/w default description 7-5 reserved - - reserved. 4 loop r/w 0 0: uart in normal condition. 1: uart is internal loop back 3 out2 r/w 0 0: all interrupt is disabled. 1: interrupt is enabled (disabled) by ier. 2 out1 r/w 0 read from msr[6] is loop back mode 1 rts r/w 0 0: rts# is forced to logic 1 1: rts# is forced to logic 0 0 dtr r/w 0 0: dtr# is forced to logic 1 1: dtr# is forced to logic 0 7.3.3.10 line status register ? base + 5 bit name r/w default description 7 rcr_err r 0 0: no error in the fifo when fifo is enabled 1: error in the fifo when fifo is enabled. 6 temt r 1 0: transmitter is in transmitting. 1: transmitter is empty. 5 thre r 1 0: transmitter holding register is not empty. 1: transmitter holding register is empty. 4 bi r 0 0: no break condition detected. 1: a break condition is detected. 3 fe r 0 0: data received has no frame error. 1: data received has frame error. 2 pe r 0 0: data received has no parity error. 1: data received has parity error.
july, 2007 v0.26p 54 f71806 1 oe r 0 0: no overrun condition occurred. 1: an overrun condition occurred. 0 dr r 0 0: no data is ready for read. 1: data is received. 7.3.3.11 modem status register ? base + 6 bit name r/w default description 7 dcd r - complement of dcd# input. in loop back mo de, this bit is equivalent to out2 in mcr. 6 ri r - complement of ri# input. in loop back mode , this bit is equivalent to out1 in mcr 5 dsr r - complement of dsr# input. in loop back mode , this bit is equivalent to dtr in mcr 4 cts r - complement of cts# input. in loop back mode , this bit is equivalent to rts in mcr 3 ddcd r 0 0: no state changed at dcd#. 1: state changed at dcd#. 2 teri r 0 0: no trailing edge at ri#. 1: a low to high transition at ri#. 1 ddsr r 0 0: no state changed at dsr#. 1: state changed at dsr#. 0 dcts r 0 0: no state changed at cts#. 1: state changed at cts#. 7.3.3.12 scratch register ? base + 7 bit name r/w default description 7-0 scr r/w 00h scratch register. 7.4 uart 2 registers 7.4.1 logic device number register logic device number register ? index 07h bit name r/w default description
july, 2007 v0.26p 55 f71806 7-0 ldn r/w 00h 00h: select fdc dev ice configuration registers. 01h: select uart 1 device configuration registers. 02h: select uart 2 device configuration registers. 03h: select parallel port devic e configuration registers. 04h: select hardware monitor device configuration registers. 05h: reserved. 06h: select gpio device c onfiguration registers. 07h: select vid device c onfiguration registers. 0ah: select pme & acpi device configuration registers. 7.4.2 uart 2 confi guration registers uart 2 device enable register ? index 30h bit name r/w default description 7-1 reserved - - reserved 0 ur2_en r/w 1 0: disable uart 2. 1: enable uart 2. base address high register ? index 60h bit name r/w default description 7-0 base_addr_hi r/w 02h the msb of uart 2 base address. base address low register ? index 61h bit name r/w default description 7-0 base_addr_lo r/w f8h the lsb of uart 2 base address. irq channel select register ? index 70h bit name r/w default description 7-4 reserved - - reserved. 3-0 selur2irq r/w 3h select t he irq channel for uart 2.
july, 2007 v0.26p 56 f71806 rs485 enable register ? index f0h bit name r/w default description 7-5 reserved - - reserved. 4 rs485_en r/w 0 0: rs232 driver. 1: rs485 driver. auto drive rts# low when transmitting data. 3 rxw4c_ir r/w 0 0: no reception delay when sir is changed form tx to rx. 1: reception delays 4 characters time when sir is changed form tx to rx. 2 txw4c_ir r/w 0 0: no transmission delay when sir is changed form rx to tx. 1: transmission delays 4 characters time when sir is changed form rx to tx. 1-0 reserved - - reserved. sir mode control register ? index f1h bit name r/w default description 7 reserved - - reserved. 6 reserved - - reserved. 5 reserved - - reserved. 4-3 irmode r/w 00 00: disable ir function. 01: disable ir function. 10: irda function, active pulse is 1.6us. 11: irda function, active pulse is 3/16 bit time. 2 hduplx r/w 1 0: sir is in full duplex mode for loopbak test. txw4c_ir and rxw4c_ir are of no use. 1: sir is in half duplex mode. 1 txinv_ir r/w 0 0: irtx is in normal condition. 1: inverse the irtx. 0 rxinv_ir r/w 0 0: irrx is in normal condition. 1: inverse the irrx. 7.4.3 device registers 7.4.3.1 receiver buffer register ? base + 0 bit name r/w default description
july, 2007 v0.26p 57 f71806 7-0 rbr r 00h the data received. read only when lcr[7] is 0 7.4.3.2 transmitter holding register ? base + 0 bit name r/w default description 7-0 thr w 00h data to be transmitted. write only when lcr[7] is 0 7.4.3.3 divisor latch (lsb) ? base + 0 bit name r/w default description 7-0 dll r/w 01h baud generator divisor low byte. access only when lcr[7] is 1. 7.4.3.4 divisor latch (msb) ? base + 1 bit name r/w default description 7-0 dlm r/w 00h baud generator divisor high byte. access only when lcr[7] is 1. 7.4.3.5 interrupt enable register ? base + 1 bit name r/w default description 7-4 reserved - - reserved. 3 edssi r/w 0 enable modem status interrupt. access only when lcr[7] is 0. 2 elsi r/w 0 enable line status error in terrupt. access only when lcr[7] is 0. 1 etbfi r/w 0 enable transmitter holding register empty interrupt. access only when lcr[7] is 0. 0 erbfi r/w 0 enable received data available interrupt. access only when lcr[7] is 0. 7.4.3.6 interrupt iden tification register ? base + 2 bit name r/w default description 7 fifo_en r 0 0: fifo is disabled 1: fifo is enabled. 6 fifo_en r 0 0: fifo is disabled 1: fifo is enabled. 5-4 reserved - - reserved. 3-1 irq_id r 000 000: interrupt is caused by modem status 001: interrupt is caused by transmitter holding register empty 010: interrupt is caused by received data available. 110: interrupt is caused by character timeout 011: interrupt is caused by line status. 0 irq_pendn r 1 1: interrupt is not pending. 0: interrupt is pending.
july, 2007 v0.26p 58 f71806 7.4.3.7 fifo control register ? base + 2 bit name r/w default description 7-6 rcv_trig w 00 00: receiver fifo trigger level is 1. 01: receiver fifo trigger level is 4. 10: receiver fifo trigger level is 8. 11: receiver fifo trigger level is 14. 5-3 reserved - - reserved. 2 clrtx r 0 reset the transmitter fifo. 1 clrrx r 0 reset the receiver fifo. 0 fifo_en r 0 0: disable fifo. 1: enable fifo. 7.4.3.8 line control register ? base + 3 bit name r/w default description 7 dlab r/w 0 0: divisor latch can?t be accessed. 1: divisor latch can be accessed via base and base+1. 6 setbrk r/w 0 0: transmitter is in normal condition. 1: transmit a break condition. 5 stkpar r/w 0 4 eps r/w 0 3 pen r/w 0 xx0: parity bit is disable 001: parity bit is odd. 011: parity bit is even 101: parity bit is logic 1 111: parity bit is logic 0 2 stb r/w 0 0: stop bit is one bit 1: when word length is 5 bit stop bit is 1.5 bit else stop bit is 2 bit 1-0 wls r/w 00 00: word length is 5 bit 01: word length is 6 bit 10: word length is 7 bit 11: word length is 8 bit 7.4.3.9 modem control register ? base + 4 bit name r/w default description 7-5 reserved - - reserved. 4 loop r/w 0 0: uart in normal condition. 1: uart is internal loop back 3 out2 r/w 0 0: all interrupt is disabled. 1: interrupt is enabled (disabled) by ier. 2 out1 r/w 0 read from msr[6] is loop back mode 1 rts r/w 0 0: rts# is forced to logic 1 1: rts# is forced to logic 0 0 dtr r/w 0 0: dtr# is forced to logic 1 1: dtr# is forced to logic 0 7.4.3.10 line status register ? base + 5 bit name r/w default description 7 rcr_err r 0 0: no error in the fifo when fifo is enabled 1: error in the fifo when fifo is enabled.
july, 2007 v0.26p 59 f71806 6 temt r 1 0: transmitter is in transmitting. 1: transmitter is empty. 5 thre r 1 0: transmitter holding register is not empty. 1: transmitter holding register is empty. 4 bi r 0 0: no break condition detected. 1: a break condition is detected. 3 fe r 0 0: data received has no frame error. 1: data received has frame error. 2 pe r 0 0: data received has no parity error. 1: data received has parity error. 1 oe r 0 0: no overrun condition occurred. 1: an overrun condition occurred. 0 dr r 0 0: no data is ready for read. 1: data is received. 7.4.3.11 modem status register ? base + 6 bit name r/w default description 7 dcd r - complement of dcd# input. in loop back mo de, this bit is equivalent to out2 in mcr. 6 ri r - complement of ri# input. in loop back mode , this bit is equivalent to out1 in mcr 5 dsr r - complement of dsr# input. in loop back mode , this bit is equivalent to dtr in mcr 4 cts r - complement of cts# input. in loop back mode , this bit is equivalent to rts in mcr 3 ddcd r 0 0: no state changed at dcd#. 1: state changed at dcd#. 2 teri r 0 0: no trailing edge at ri#. 1: a low to high transition at ri#. 1 ddsr r 0 0: no state changed at dsr#. 1: state changed at dsr#. 0 dcts r 0 0: no state changed at cts#. 1: state changed at cts#. 7.4.3.12 scratch register ? base + 7 bit name r/w default description 7-0 scr r/w 00h scratch register.
july, 2007 v0.26p 60 f71806 7.5 parallel port registers 7.5.1 logic device number register logic device number register ? index 07h bit name r/w default description 7-0 ldn r/w 00h 00h: select fdc dev ice configuration registers. 01h: select uart 1 device configuration registers. 02h: select uart 2 device configuration registers. 03h: select parallel port devic e configuration registers. 04h: select hardware monitor device configuration registers. 05h: reserved. 06h: select gpio device c onfiguration registers. 07h: select vid device c onfiguration registers. 0ah: select pme & acpi device configuration registers. 7.5.2 parallel port configuration register parallel port device enable register ? index 30h bit name r/w default description 7-1 reserved - - reserved 0 prt_en r/w 1 0: disable parallel port. 1: enable parallel port. base address high register ? index 60h bit name r/w default description 7-0 base_addr_hi r/w 03h the msb of parallel port base address. base address low register ? index 61h bit name r/w default description 7-0 base_addr_lo r/w 78h the lsb of parallel port base address.
july, 2007 v0.26p 61 f71806 irq channel select register ? index 70h bit name r/w default description 7-4 reserved - - reserved. 3-0 selprtirq r/w 7h select the irq channel for parallel port. dma channel select register ? index 74h bit name r/w default description 7-5 reserved - - reserved. 4 ecp_dma_mode r/w 0 0: non-burst mode dma. 1: enable burst mode dma. 3 reserved - - reserved. 2-0 selprtdma r/w 011 select the dma channel for parallel port. prt mode select register ? index f0h bit name r/w default description 7 reserved - - reserved. 6-3 ecp_fifo_thr r/w 1000 ecp fifo threshold. 2-0 prt_mode r/w 010 000: standard and bi-direction (spp) mode. 001: epp 1.9 and spp mode. 010: ecp mode (default). 011: ecp and epp 1.9 mode. 100: printer mode. 101: epp 1.7 and spp mode. 110: reserved. 111: ecp and epp1.7 mode. 7.5.3 device registers 7.5.3.1 parallel port data register ? base + 0 bit name r/w default description 7-0 data r/w 00h the output data to dr ive the parallel port data lines. 7.5.3.2 ecp address fifo register ? base + 0 bit name r/w default description
july, 2007 v0.26p 62 f71806 7-0 ecp_afifo r/w 00h access only in ecp parallel port mode and the ecp_mode programmed in the extended control register is 011. the data written to this register is placed in the fifo and tagged as an address/rle. it is auto transmitted by the hardware. the operation is only defined for forward direction. it divide into two parts : bit 7 : 0: bits 6-0 are run length, indicating how many times the next byte to appear (0 = 1time, 1 = 2times, 2 = 3times and so on). 1: bits 6-0 are a ecp address. bit 6-0 : address or rle depends on bit 7. 7.5.3.3 device status register ? base + 1 bit name r/w default description 7 busy_n r - inverted version of parallel port signal busy. 6 ack_n r - version of parallel port signal ack#. 5 perror r - version of parallel port signal pe. 4 select r - version of parallel port signal slct. 3 err_n r - version of parallel port signal err#. 2-1 reserved r 11 reserved. return 11b when read. 0 tmout r - this bit is valid only in epp mode. return 1 when in other modes. it indicates that a 10us time out has occurred on the epp bus. 0: no time out error. 1: time out error occurred, write 1 to clear. 7.5.3.4 device control register ? base + 2 bit name r/w default description 7-6 reserved - 11 reserved. return 11b when read. 5 dir r/w 0 0: the parallel port is in output mode. 1: the parallel port is in input mode. it is auto reset to 0 when in spp mode. 4 ackirq_en r/w 0 enable an interr upt at the rising edge of ack#. 3 slin r/w 0 inverted and then drives the parallel port signal slin#. when read, the status of inverted slin# is return. 2 init_n r/w 0 drives the parallel port signal init#. when read, the status of init# is return. 1 afd r/w 0 inverted and then drives the parallel port signal afd#. when read, the status of inverted afd# is return. 0 stb r/w 0 inverted and then drives the parallel port signal stb#. when read, the status of inverted stb# is return.
july, 2007 v0.26p 63 f71806 7.5.3.5 epp address register ? base + 3 bit name r/w default description 7-0 epp_addr r/w 00h write this register will cause the hardwar e to auto transmit the written data to the device with the epp address write protocol. read this register will cause the hardwar e to auto receive data from the device by with the epp address read protocol. 7.5.3.6 epp data register ? base + 4 ? base + 7 bit name r/w default description 7-0 epp_data r/w 00h write this register will cause the hardwar e to auto transmit the written data to the device with the epp data write protocol. read this register will cause the hardwar e to auto receive data from the device by with the epp data read protocol. 7.5.3.7 parallel port data fifo ? base + 400h bit name r/w default description 7-0 c_fifo r/w 00h data written to this fifo is auto transmitted by the hardware to the device by using standard parallel port protocol. it is only valid in ecp and the ecp_mode is 010b.the operation is only for forward direction. 7.5.3.8 ecp data fifo ? base + 400h bit name r/w default description 7-0 ecp_dfifo r/w 00h data written to this fifo when dir is 0 is auto transmitted by the hardware to the device by using ecp parallel port protocol. data is auto read from device into the fifo when dir is 1 by the hardware by using ecp parallel port protocol. read the fifo will return the content to the system. it is only valid in ecp and the ecp_mode is 011b. 7.5.3.9 ecp test fifo ? base + 400h bit name r/w default description 7-0 t_fifo r/w 00h data may be read, written from system to the fifo in any direction. but no hardware handshake occurred on the parallel port lines. it could be used to test the empty, full and threshold of the fifo. it is only valid in ecp and the ecp_mode is 110b. 7.5.3.10 ecp configur ation register a ? base + 400h bit name r/w default description
july, 2007 v0.26p 64 f71806 7 irq_mode r 0 0: interrupt is isa pulse. 1: interrupt is isa level. only valid in ecp and ecp_mode is 111b. 6-4 impid r 001 000: the design is 16-bit implementation. 001: the design is 8-bit implementation (default). 010: the design is 32-bit implementation. 011-111: reserved. only valid in ecp and ecp_mode is 111b. 3 reserved - - reserved. 2 bytetran_n r 1 0: when transmitting there is 1 by te waiting in the transceiver that does not affect the fifo full condition. 1: when transmitting the state of the full bit includes the byte being transmitted. only valid in ecp and ecp_mode is 111b. 1-0 reserved r 00 return 00 when read. only valid in ecp and ecp_mode is 111b. 7.5.3.11 ecp configur ation register b ? base + 401h bit name r/w default description 7 comp r 0 0: only send uncompressed data. 1: compress data before sending. only valid in ecp and ecp_mode is 111b. 6 reserved r 1 reserved. return 1 when read. only valid in ecp and ecp_mode is 111b. 5-3 ecp_irq_ch r 001 000: the interrupt selected with jumper. 001: select irq 7 (default). 010: select irq 9. 011: select irq 10. 100: select irq 11. 101: select irq 14. 110: select irq 15. 111: select irq 5. only valid in ecp and ecp_mode is 111b. 2-0 ecp_dma_ch r 011 return the dma channel of ecp parallel port. only valid in ecp and ecp_mode is 111b. 7.5.3.12 extended control register ? base + 402h bit name r/w default description
july, 2007 v0.26p 65 f71806 7-5 ecp_mode r/w 000 000: spp mode. 001: ps/2 parallel port mode. 010: parallel port data fifo mode. 011: ecp parallel port mode. 100: epp mode. 101: reserved. 110: test mode. 111: configuration mode. only valid in ecp. 4 errintr_en r/w 0 0: disable the inte rrupt generated on the falling edge of err#. 1: enable the interrupt generated on the falling edge of err#. 3 damen r/w 0 0: disable dma. 1: enable dma. dma starts when serviceintr is 0. 2 serviceintr r/w 1 0: enable the following case of interrupt. dmaen = 1: dma mode. dmaen = 0, dir = 0: set to 1 whenever there are writeintrthreshold or more bytes are free in the fifo. dmaen = 0, dir = 0: set to 1 whenever there are readintrthreshold or more bytes are valid to be read in the fifo. 1 fifofull r 0 0: the fifo has at least 1 free byte. 1: the fifo is completely full. 0 fifoempty r 0 0: the fifo contains at least 1 byte. 1: the fifo is completely empty. 7.6 hardware monitor registers 7.6.1 logic device number register logic device number register ? index 07h bit name r/w default description
july, 2007 v0.26p 66 f71806 7-0 ldn r/w 00h 00h: select fdc dev ice configuration registers. 01h: select uart 1 device configuration registers. 02h: select uart 2 device configuration registers. 03h: select parallel port devic e configuration registers. 04h: select hardware monitor device configuration registers. 05h: reserved. 06h: select gpio device c onfiguration registers. 07h: select vid device c onfiguration registers. 0ah: select pme & acpi device configuration registers. 7.6.2 hardware monitor configuration registers hardware monitor device enable register ? index 30h bit name r/w default description 7-1 reserved - - reserved 0 hm_en r/w 0 0: disable hardware monitor. 1: enable hardware monitor. base address high register ? index 60h bit name r/w default description 7-0 base_addr_hi r/w 02h the msb of hardware monitor base address. base address low register ? index 61h bit name r/w default description 7-0 base_addr_lo r/w 95h the lsb of hardware monitor base address. irq channel select register ? index 70h bit name r/w default description 7-4 reserved - - reserved. 3-0 selhmirq r/w 0000 select the irq channel for hardware monitor.
july, 2007 v0.26p 67 f71806 7.6.3 device registers 7.6.3.1 start_stop control register ? index 00h bit name r/w default description 7 init r/w 0 set one restores power on default va lue to all registers. this bit clears itself since the power on default is zero. 6 soft_pwdn r/w 0 set this bit to 1 will power down a/d converter circuit. default is 0. 5-1 reserved - - reserved 0 start r/w 1 a one enables startup of monitoring operations; a zero puts the part in standby mode. 7.6.3.2 temperature mode control register ? index 01h bit name r/w default description 7-6 temperature fault queue r/w 00 this value stands for how many times of successive temperature fault can be tolerated. 00: 1 times. 01: 2 times. 10: 4 times. 11: 8 times. 5-4 reserved - - reserved 3 comb_level r/w 1 set to 1, enable comb filter. se t to 0, disable comb filter. comb filter is only applied to bjt thermal diode mode. if temperature select thermistor mode, the comb filter will not work on it. 2 t3_mode r/w 0 set to 1, select t3 as connected to a bjt thermal diode. at this mode, t3 detected temperature ranges from 0c ~ 140c. set to 0, select t3 as connected to a thermistor. at this mode, t3 detected temperature ranges from 0c ~ 127c. 1 t2_mode r/w 0 set to 1, select t2 as connected to a bjt thermal diode. at this mode, t2 detected temperature ranges from 0c ~ 140c. set to 0, select t2 as connected to a thermistor. at this mode, t2 detected temperature ranges from 0c ~ 127c. 0 t1_mode r/w 0 set to 1, select t1 as connected to a bjt thermal diode. at this mode, t1 detected temperature ranges from 0c ~ 140c. set to 0, select t1 as connected to a thermistor. at this mode, t1 detected temperature ranges from 0c ~ 127c. 7.6.3.3 adc_clk freque ncy control register ? index 02h bit name r/w default description 7-2 reserved - - reserved 1-0 adc_clk_sel r/w 00 select adc clock frequency. 00 : 12.8k(default) 01 : 6.4k 10 : 3.2k 11 : 1.6k
july, 2007 v0.26p 68 f71806 7.6.3.4 fan1 full speed count register 0 ? index 0ah bit name r/w default description 7-0 f1_full(msb) r 00h when power on, the fanpwm1 will output full duty cycle (ffh) to enable system fan. after 10 seconds when detecting fanin signal , assuming the fan has been fully turned on, the fan sp eed count detected will be recorded in the register. if there is no signal on fanin after power on, the pwmout1 will keep outputting ffh duty cycle. 7.6.3.5 fan1 full speed count register 1 ? index 0bh bit name r/w default description 7-0 f1_full(lsb) r ffh when power on, the fanpwm1 will output full duty cycle (ffh) to enable system fan. after 10 seconds when detecting fanin signal , assuming the fan has been fully turned on, the fan sp eed count detected will be recorded in the register. if there is no signal on fanin after power on, the pwmout1 will keep outputting ffh duty cycle. 7.6.3.6 fan2 full speed count register 0 ? index 0ch bit name r/w default description 7-0 f2_full(msb) r 0fh when power on, the fanpwm2 will output full duty cycle (ffh) to enable system fan. after 10 seconds when detecting fanin signal , assuming the fan has been fully turned on, the fan sp eed count detected will be recorded in the register. if there is no signal on fanin2 after power on, the pwmout2 will keep outputting ffh duty cycle. 7.6.3.7 fan2 full speed count register 1 ? index 0dh bit name r/w default description 7-0 f2_full(lsb) r ffh when power on, the fanpwm2 will output full duty cycle (ffh) to enable system fan. after 10 seconds when detecting fanin signal , assuming the fan has been fully turned on, the fan sp eed count detected will be recorded in the register. if there is no signal on fanin1 after power on, the pwmout2 will keep outputting ffh duty cycle. 7.6.3.8 fan3 full speed count register 0 ? index 0eh bit name r/w default description 7-0 f3_full(msb) r 0fh when power on, the fanpwm3 will output full duty cycle (ffh) to enable system fan. after 10 seconds when detecting fanin signal , assuming the fan has been fully turned on, the fan sp eed count detected will be recorded in the register. if there is no signal on fanin2 after power on, the pwmout3 will keep outputting ffh duty cycle.
july, 2007 v0.26p 69 f71806 7.6.3.9 fan3 full speed count register 1 ? index 0fh bit name r/w default description 7-0 f3_full(lsb) r ffh when power on, the fanpwm3 will output full duty cycle (ffh) to enable system fan. after 10 seconds when detecting fanin signal , assuming the fan has been fully turned on, the fan sp eed count detected will be recorded in the register. if there is no signal on fanin3 after power on, the pwmout3 will keep outputting ffh duty cycle. 7.6.3.10 value ram ? index 10h - 2fh, 40h - 59h in the following table, the unit of voltage reading/limit is 8mv. the unit of temperature reading/limit is 1 o c. address 10-3f r/w description 0ah ro fan1 full speed count reading [11:8] 0bh ro fan1 full speed count reading [7:0] 0ch ro fan2 full speed count reading [11:8] 0dh ro fan2 full speed count reading [7:0] 0eh ro fan3 full speed count reading [11:8] 0fh ro fan3 full speed count reading [7:0] 10h ro vcc reading. this reading is the divided voltage of vcc inside the chip. 11h ro vin1 reading. 12h ro vin2 reading. 13h ro vin3 reading. 14h ro vin4 reading. 15h ro vin5 reading. 16h ro vin6 reading. 17h ro vin7 reading. 18h ro vin8 reading. 19h ro vsb reading. this reading is the divided voltage of vsb inside the chip. 1ah ro vbat reading. this reading is the divided voltage of vbat inside the chip. 1bh ro t1 temperature reading. 1ch ro t2 temperature reading. 1dh ro t3 temperature reading. 1eh reserved 20h ro fan1 count reading (msb) 21h ro fan1 count reading (lsb) 22h ro fan2 count reading (msb) 23h ro fan2 count reading (lsb) 24h ro fan3 count reading (msb) 25h ro fan3 count reading (lsb) 26h ~ 27h reserved 28h r/w fan1 count limit. (msb) 29h r/w fan1 count limit. (lsb) 2ah r/w fan2 count limit. (msb) 2bh r/w fan2 count limit. (lsb). 2ch r/w fan3 count limit. (msb) 2dh r/w fan3 count limit. (lsb) 2eh r/w vbat high limit. this limit should correspond to the divided voltage. 2fh r/w vbat low limit. this limit should correspond to the divided voltage. 40h r/w vcc high limit. this limit should correspond to the divided voltage. 41h r/w vcc low limit. this limit should correspond to the divided voltage.
july, 2007 v0.26p 70 f71806 42h r/w vin1 high limit. 43h r/w vin1 low limit. 44h r/w vin2 high limit. 45h r/w vin2 low limit. 46h r/w vin3 high limit. 47h r/w vin3 low limit. 48h r/w vin4 high limit. 49h r/w vin4 low limit. 4ah r/w vin5 high limit. 4bh r/w vin5 low limit. 4ch r/w vin6 high limit. 4dh r/w vin6 low limit. 4eh r/w vin7 high limit. 4fh r/w vin7 low limit. 50h r/w vin8 high limit. 51h r/w vin8 low limit. 52h r/w vsb high limit. this limit should correspond to the divided voltage. 53h r/w vsb low limit. this limit should correspond to the divided voltage. 54h r/w t1 high limit. 55h r/w t1 low limit. 56h r/w t2 high limit. 57h r/w t2 low limit. 58h r/w t3 high limit. 59h r/w t3 low limit. 7.6.3.11 interrupt enable control register 1 ? index 30h bit name r/w default description 7 en_vin7 r/w 0 set to 1, enables vin7 abnormal interrupt. 6 en_vin6 r/w 0 set to 1, enables vin6 abnormal interrupt. 5 en_vin5 r/w 0 set to 1, enables vin5 abnormal interrupt. 4 en_vin4 r/w 0 set to 1, enables vin4 abnormal interrupt. 3 en_vin3 r/w 0 set to 1, enables vin3 abnormal interrupt. 2 en_vin2 r/w 0 set to 1, enables vin2 abnormal interrupt. 1 en_vin1 r/w 0 set to 1, enables vin1 abnormal interrupt. 0 en_3vdd r/w 0 set to 1, enables 3vdd abnormal interrupt. 7.6.3.12 interrupt enable control register 2 ? index 31h bit name r/w default description 7-6 reserved - - 5 en_t3 r/w 0 set to 1, enables t3 abnormal interrupt. 4 en_t2 r/w 0 set to 1, enables t2 abnormal interrupt. 3 en_t1 r/w 0 set to 1, enables t1 abnormal interrupt. 2 en_vbat r/w 0 set to 1, enables vbat abnormal interrupt. 1 en_vsb r/w 0 set to 1, enables vsb abnormal interrupt. 0 en_vin8 r/w 0 set to 1, enables vin8 abnormal interrupt.
july, 2007 v0.26p 71 f71806 7.6.3.13 interrupt enable control register 3 ? index 32h bit name r/w default description 7 reserved - - 6 en_case r/w 0 set to 1, enables chassis open interrupt. 5 en_fan3_tar r/w 0 set to 1, enables fan3 target speed mismatched interrupt when fanpwm3 duty-cycle is 100%. 4 en_fan2_tar r/w 0 set to 1, enables fan2 target speed mismatched interrupt when fanpwm2 duty-cycle is 100%. 3 en_fan1_tar r/w 0 set to 1, enables fan1 target speed mismatched interrupt when fanpwm1 duty-cycle is 100%. 2 en_fan3_lmt r/w 0 set to 1, enables fan3 abnormal interrupt. 1 en_fan2_lmt r/w 0 set to 1, enables fan2 abnormal interrupt. 0 en_fan1_lmt r/w 0 set to 1, enables fan1 abnormal interrupt. 7.6.3.14 interrupt st atus register 1 ? index 33h bit name r/w default description 7 vin7_sts r/w 0 a one indicates vin7 reaches its high or low limit. write 1 to clear this bit, write 0 will be ignored. 6 vin6_sts r/w 0 a one indicates vin6 reaches its high or low limit. write 1 to clear this bit, write 0 will be ignored. 5 vin5_sts r/w 0 a one indicates vin5 reaches its high or low limit. write 1 to clear this bit, write 0 will be ignored. 4 vin4_sts r/w 0 a one indicates vin4 reaches its high or low limit. write 1 to clear this bit, write 0 will be ignored. 3 vin3_sts r/w 0 a one indicates vin3 reaches its high or low limit. write 1 to clear this bit, write 0 will be ignored. 2 vin2_sts r/w 0 a one indicates vin2 reaches its high or low limit. write 1 to clear this bit, write 0 will be ignored. 1 vin1_sts r/w 0 a one indicates vin1 reaches its high or low limit. write 1 to clear this bit, write 0 will be ignored. 0 3vdd_sts r/w 0 a one indicates 3vdd reaches its high or low limit. write 1 to clear this bit, write 0 will be ignored. 7.6.3.15 interrupt st atus register 2 ? index 34h bit name r/w default description 7-6 reserved - - 5 t3_sts r/w 0 a one indicates t3 reaches its high or low limit. write 1 to clear this bit, write 0 will be ignored. 4 t2_sts r/w 0 a one indicates t2 reaches its high or low limit. write 1 to clear this bit, write 0 will be ignored. 3 t1_sts r/w 0 a one indicates t1 reaches its high or low limit. write 1 to clear this bit, write 0 will be ignored. 2 vbat_sts r/w 0 a one indicates vbat reaches its high or low limit. write 1 to clear this bit, write 0 will be ignored.
july, 2007 v0.26p 72 f71806 1 vsb_sts r/w 0 a one indicates vsb reaches its high or low limit. write 1 to clear this bit, write 0 will be ignored. 0 vin8_sts r/w 0 a one indicates vin8 reaches its high or low limit. write 1 to clear this bit, write 0 will be ignored. 7.6.3.16 interrupt st atus register 3 ? index 35h bit name r/w default description 7 reserved - - 6 caseopen 0 a one indicates that chassis has been opened. 5 fan3_tar_sts r/w 0 a one indicates fan3 can not reach the expect count in time. the time is defined by fan3 fault time registers. 4 fan2_tar_sts r/w 0 a one indicates fan2 can not reach the expect count in time. the time is defined by fan2 fault time registers. 3 fan1_tar_sts r/w 0 a one indicates fan1 can not reach the expect count in time. the time is defined by fan1 fault time registers. 2 fan3_sts r/w 0 a one indicates fan3 reaches its high or low limit. write 1 to clear this bit, write 0 will be ignored. 1 fan2_sts r/w 0 a one indicates fan2 reaches its high or low limit. write 1 to clear this bit, write 0 will be ignored. 0 fan1_sts r/w 0 a one indicates fan1 reaches its high or low limit. write 1 to clear this bit, write 0 will be ignored. 7.6.3.17 real_time st atus register 1 ? index 36h bit name r/w default description 7 vin7_rt r 0 a one indicates vin7 is at abnormal range. 6 vin6_rt r 0 a one indicates vin6 is at abnormal range. 5 vin5_rt r 0 a one indicates vin5 is at abnormal range. 4 vin4_rt r 0 a one indicates vin4 is at abnormal range. 3 vin3_rt r 0 a one indicates vin3 is at abnormal range. 2 vin2_rt r 0 a one indicates vin2 is at abnormal range. 1 vin1_rt r 0 a one indicates vin1 is at abnormal range. 0 3vdd_rt r 0 a one indicates 3vdd is at abnormal range. 7.6.3.18 real_time st atus register 2 ? index 37h bit name r/w default description 7-6 reserved - - 5 t3_rt r 0 a one indicates t3 exceeds its high limit. 4 t2_rt r 0 a one indicates t2 exceeds its high limit. 3 t1_rt r 0 a one indicates vbat exceeds its high limit. 2 vbat_rt r 0 a one indicates vbat exceeds its high limit. 1 vsb_rt r 0 a one indicates vsb exceeds its high limit.
july, 2007 v0.26p 73 f71806 0 vin8_rt r 0 a one indicates vin8 exceeds its high limit. 7.6.3.19 real_time st atus register 3 ? index 38h bit name r/w default description 7 reserved - - 6 caseopen r 0 a one indicates that chassis is opened. 5 fan3_tar_rt r 0 a one indicates fan3 can not reach the expect count in time when fanpwm3 duty-cycle is 100%. the time is defined by fan3 fault time registers. after fan3 reaches the expect count, the bit will be set to 0. 4 fan2_tar_rt r 0 a one indicates fan2 can not reach the expect count in time when fanpwm2 duty-cycle is 100%. the time is defined by fan2 fault time registers. after fan2 reaches the expect count, the bit will be set to 0. 3 fan1_tar_rt r 0 a one indicates fan1 can not reach the expect count in time when fanpwm1 duty-cycle is 100%. the time is defined by fan1 fault time registers. after fan1 reaches the expect count, the bit will be set to 0. 2 fan3_rt r 0 a one indicates fan3 is at abnormal range. 1 fan2_rt r 0 a one indicates fan2 is at abnormal range. 0 fan1_rt r 0 a one indicates fan1 is at abnormal range. 7.6.3.20 vin_fault mode register 3 ? index 39h bit name r/w default description 7 reserved r/w 0 reserved. 6-4 reserved - - reserved. 3 vin4f_sel r 0 set to 1, once vin4_fault is asserted, it will not be de-asserted when vin4 is back to normal range. set to 0, vin4_fault is asserted/de-asse rted according to its value whether is out of high/low limit. 2 vin3f_sel r 0 set to 1, once vin3_fault is asserted, it will not be de-asserted when vin4 is back to normal range. set to 0, vin3_fault is asserted/de-asse rted according to its value whether is out of high/low limit. 1 vin2f_sel r 0 set to 1, once vin2_fault is asserted, it will not be de-asserted when vin4 is back to normal range. set to 0, vin2_fault is asserted/de-asse rted according to its value whether is out of high/low limit. 0 vin1f_sel r 0 set to 1, once vin1_fault is asserted, it will not be de-asserted when vin4 is back to normal range. set to 0, vin1_fault is asserted/de-asse rted according to its value whether is out of high/low limit. 7.6.3.21 vin_fault st atus register ? index 3ah bit name r/w default description 7 reserved r/w 0 reserved. 6-4 reserved - -
july, 2007 v0.26p 74 f71806 3 sts_vin4_fault r/w 0 read one indicates that vin4 is out of it s high/low limit. write 1 to clear this status. 2 sts_vin3_fault r/w 0 read one indicates that vin3 is out of it s high/low limit. write 1 to clear this status. 1 sts_vin2fault r/w 0 read one indicates that vin2 is out of it s high/low limit. write 1 to clear this status. 0 sts_vin1_fault r/w 0 read one indicates that vin1 is out of it s high/low limit. write 1 to clear this status. 7.6.3.22 t_fault control register ? index 3bh bit name r/w default description 7-3 reserved - - 2 en_t3_fault r/w 0 set to 1, enable temperature 3( vt3)fault through pin ovt_n. 1 en_t2_fault r/w 0 set to 1, enable temperature 2(vt 2) fault through pin ovt_n. 0 en_t1_fault r/w 0 set to 1, enable temper ature 1(vt1) fault through pin ovt_n. 7.6.3.23 case open status clear register ? index 3ch bit name r/w default description 7-1 reserved - - 0 clr_intrude w 0 write 1 to clear the latched caseopen event status. 7.6.3.24 beep control register 1 ? index 3dh bit name r/w default description 7 en_vin7_beep r/w 0 write 1 to enable the beep ala rm for vin7 abnormal event. write 0 to disable it. 6 en_vin6_beep r/w 0 write 1 to enable the beep ala rm for vin6 abnormal event. write 0 to disable it. 5 en_vin5_beep r/w 0 write 1 to enable the beep ala rm for vin5 abnormal event. write 0 to disable it. 4 en_vin4_beep r/w 0 write 1 to enable the beep ala rm for vin4 abnormal event. write 0 to disable it. 3 en_vin3_beep r/w 0 write 1 to enable the beep ala rm for vin3 abnormal event. write 0 to disable it. 2 en_vin2_beep r/w 0 write 1 to enable the beep ala rm for vin2 abnormal event. write 0 to disable it. 1 en_vin1_beep r/w 0 write 1 to enable the beep ala rm for vin1 abnormal event. write 0 to disable it. 0 en_vcc_beep r/w 0 write 1 to enable the beep alarm for 3vdd abnormal event. write 0 to disable it. 7.6.3.25 beep control register 2 ? index 3eh bit name r/w default description 7-6 reserved - - 5 en_t3_beep r/w 0 write 1 to enable the beep alarm for t3 abnormal event. write 0 to disable it 4 en_t2_beep r/w 0 write 1 to enable the beep alarm for t2 abnormal event. write 0 to disable it 3 en_t1_beep r/w 0 write 1 to enable the beep alarm for t1 abnormal event. write 0 to disable it
july, 2007 v0.26p 75 f71806 2 en_vbat_beep r/w 0 write 1 to enable the beep al arm for vbat abnormal event. write 0 to disable it 1 en_vin7_beep r/w 0 write 1 to enable the beep alarm for vsb abnormal event. write 0 to disable it 0 en_vin8_beep r/w 0 write 1 to enable the beep ala rm for vin8 abnormal event. write 0 to disable it 7.6.3.26 beep control register 3 ? index 3fh bit name r/w default description 7 reserved - - 6 en_case_beep r/w 0 write 1 to enable the beep alarm for caseopen abnormal event. write 0 to disable it 5 en_fan3_tar_ beep r/w 0 write 1 to enable the beep alarm for fan3 target-not-reached event. write 0 to disable it 4 en_fan2_tar_ beep r/w 0 write 1 to enable the beep alarm for fan2 target-not-reached event. write 0 to disable it 3 en_fan1_tar_bee p r/w 0 write 1 to enable the beep alarm for fan1 target-not-reached event. write 0 to disable it 2 en_fan3_lmt_bee p r/w 0 write 1 to enable the beep alarm for fa n3 under-limit event. write 0 to disable it 1 en_fan2_lmt_bee p r/w 0 write 1 to enable the beep alarm for fa n2 under-limit event. write 0 to disable it 0 en_fan1_lmt_bee p r/w 0 write 1 to enable the beep alarm for fa n1 under-limit event. write 0 to disable it 7.6.3.27 fan1 operating cont rol register -- index 60h bit name r/w default description 7 fan1_skip r - when this bit is set to 1, fan1 is not monitored. when this bit is set to 0, fan1 is monitored. 6 reserved - - 5 fan1_force_moni tor r/w 0 set to 1, fan1 speed is monitored every monitor cycle even the fan is stopped. set to 0, fan1 speed will not be monitored at the next monitor cycle if the fan is stopped. 4 fan1_dc_mode r/w 0 set to 1, fan1 contro l is set to dc mode. set to 0, fan1 control is set to pwm duty-cycle mode. 3 f1_latch_full r/w 0 set to 1, current fan1 count will be bypass to fan1_full_speed. 2 f1_keep_stop r/w 0 set to 1, keep fanpwm1 duty-cycle decrease to stop duty and hold. 1-0 f1_mode r/w 00 00: fan1 operates in speed mode. fanpwm duty-cycle is automatically adjusted according to fan expect register. 01: fan1 operates in temperature mode. fanpwm duty-cycle is automatically adjusted accordi ng to current temperature, 1x: fan1 operates in manual mode. software set the fanpwm duty-cycle directly. 7.6.3.28 fanpwm1 start up duty-cycle ? index 61h bit name r/w default description 7-0 f1_start_duty[9:2] r/w 30h fanpwm1 will increasing duty-cycle from 0 to this valuedirectly.
july, 2007 v0.26p 76 f71806 7.6.3.29 fanpwm1 stop duty-cycle ? index 62h bit name r/w default description 7-0 f1_stop_duty[9:2] r/w 25h fanpwm1 will decreasing duty-cycle to 0 from this value directly or keep duty-cycle in this value when fan1_keep_stop set to 1. 7.6.3.30 fanpwm1 output frequency control ? index 63h bit name r/w default description 7 pwm1_div[7] r/w set to 1, pr eclk(pre-clock) = 48m hz ; set to 0, preclk = 1m hz . 6-0 pwm1_div[6:0] r/w 80h pre-divisor of preclk. fanpwm1 output frequency = 256 ) - (pr ? divisor e preclk so, pwm frequency ranges from 30.5hz~187.5khz 7.6.3.31 fanpwm1 step contro l register -- index 64h bit name r/w default description 7-4 f1_up_step r/w this value determines the increasing speed of pwm1_duty. 3-0 f1_down_step r/w 00h this value determines the decreasing speed of pwm1_duty. 7.6.3.32 fan1_fault time register ? index 65h bit name r/w default description 7-0 f1_fault_time r/w 03h this register determines t he time for fan to chase to the expect speed. two conditions cause fan fault event: (1). when pwm_duty reaches ffh, if the fan speed count can?t reach the fan expect count in the time. (2). when pwm_duty reaches 00h, if the fan speed count can?t reach the fan expect count in the time. the unit of this register is 1 sec ond. the default value is 3 seconds. 7.6.3.33 fan1 expect c ount register---index 69h bit name r/w default description 7-4 reserved - 3-0 f1_expect (msb) r 00h user expect fan1 count value, program this register to control the expect fan1 speed 7.6.3.34 fan1 expect c ount register-- index 6ah p bit name r/w default description 7-0 f1_expect (lsb) r 00h user expect fan1 count value, program this register to control the expect fan1 speed.
july, 2007 v0.26p 77 f71806 7.6.3.35 fan1 pwm_duty -- index 6bh bit name r/w default description 7-0 pwm_duty1 r/w ffh when fan1 control is at pw m duty-cycle mode, this value represents the duty-cycle. when fan1 control is at dc mode, th is value represents the dc voltage output. each step (lsb) is vcc / 256. this register is programmable at manual mode. at speed or temperature mode, th is register reflects current fanpwm1 duty-cycle. 7.6.3.36 fan2 operating cont rol register -- index 70h bit name r/w default description 7 fan2_skip r - when this bit is set to 1, fan2 is not monitored. when this bit is set to 0, fan2 is monitored. 6 reserved - - reserved. 5 fan2_force_moni tor r/w 0 set to 1, fan2 speed is monitored every monitor cycle even the fan is stopped. set to 0, fan2 speed will not be monitored at the next monitor cycle if the fan is stopped. 4 fan2_dc_mode r/w 0 set to 1, fan2 contro l is set to dc mode. set to 0, fan2 control is set to pwm duty-cycle mode. 3 f2_latch_full r/w 0 set to 1, current fa n2 count will be bypass to f2_full_speed. 2 f2_keep_stop r/w 0 set to 1, keep fanpwm2 duty-cycle decrease to stop duty and hold. 1-0 f2_mode r/w 00 00: fan2 operates in speed mode. fanpwm duty-cycle is automatically adjusted according to fan expect register. 01: fan2 operates in temperature mode. fanpwm duty-cycle is automatically adjusted accordi ng to current temperature, 1x: fan2 operates in manual mode. software set the fanpwm duty-cycle directly. 7.6.3.37 fanpwm2 start up duty-cycle ? index 71h bit name r/w default description 7-0 f2_start_duty r/w 30h fanpwm2 will increase duty-cycle from 0 to this value directly. 7.6.3.38 fanpwm2 stop duty-cycle ? index 72h bit name r/w default description 7-0 f2_stop_duty r/w 25h fanpwm2 will decreasing duty-cy cle to 0 from this value directly or keep duty-cycle in this value when f2_keep_stop set to 1. 7.6.3.39 fanpwm2 output frequency control ? index 73h bit name r/w default description 7 pwm2_div[7] r/w set to 1, pr eclk(pre-clock) = 48m hz ; set to 0, preclk = 1m hz . 6-0 pwm2_div[6:0] r/w 80h pre-divisor of preclk.
july, 2007 v0.26p 78 f71806 fanpwm2 output frequency = 256 ) (pr ? ? divisor e preclk so, pwm frequency ranges from 30.5hz~187.5khz 7.6.3.40 fanpwm2 step contro l register -- index 74h bit name r/w default description 7-4 f 2_up_step r/w this value determines the increasing speed of pwm2_duty. 3-0 f 2_down _ step r/w 00h this value determines the decreasing speed of pwm2_duty 7.6.3.41 fan2_fault time register ? index 75h bit name r/w default description 7-0 f2_fault_time r/w 03h this register determines t he time for fan to chase to the expect speed. two conditions cause fan fault event: (1). when pwm_duty reaches ffh, if the fan speed count can?t reach the fan expect count in the time. (2). when pwm_duty reaches 00h, if the fan speed count can?t reach the fan expect count in the time. the unit of this register is 1 sec ond. the default value is 180 seconds. 7.6.3.42 fan2 expect c ount register-- index 79h bit name r/w default description 7-4 reserved - 3-0 f2_expect (msb) r 00h user expect fan2 count value, program th is register to control the expect fan2 speed 7.6.3.43 fan2 expect c ount register-- index 7ah bit name r/w default description 7-0 f2_expect (lsb) r 00h user expect fan2 count valu e, program this register to control the expect fan2 speed. 7.6.3.44 fan2 pwm_duty -- index 7bh bit name r/w default description 7-0 pwm_duty2 r/w ffh when fan2 control is at pw m duty-cycle mode, this value represents the duty-cycle. when fan2 control is at dc mode, th is value represents the dc voltage output. each step (lsb) is vcc / 256. this register is programmable at manual mode. at speed or temperature mode, th is register reflects current fanpwm1 duty-cycle.
july, 2007 v0.26p 79 f71806 7.6.3.45 fan3 operating cont rol register -- index 80h bit name r/w default description 7 fan3_skip r - when this bit is set to 1, fan3 is not monitored. when this bit is set to 0, fan3 is monitored. 6 reserved - - 5 fan3_force_moni tor r/w 0 set to 1, fan3 speed is monitored every monitor cycle even the fan is stopped. set to 0, fan3 speed will not be monitored at the next monitor cycle if the fan is stopped. 4 fan3_dc_mode r/w 0 set to 1, fan3 contro l is set to dc mode. set to 0, fan3 control is set to pwm duty-cycle mode. 3 f3_latch_full r/w 0 set to 1, current fan3 count will be bypass to f3_full_speed. 2 f3_keep_stop r/w 0 set to 1, keep fanpwm3 duty-cycle decrease to stop duty and hold. 1-0 f3_mode r/w 00 00: fan3 operates in speed mode. fanpwm3 duty-cycle is automatically adjusted according to fan expect register. 01: fan3 operates in temperature mode. fanpwm3 duty-cycle is automatically adjusted accordi ng to current temperature, 1x: fan3 operates in manual mode. software set the fanpwm3 duty-cycle directly. 7.6.3.46 fanpwm3 start up duty-cycle ? index 81h bit name r/w default description 7-0 f3_start_duty r/w 30h fanpwm3 will increase duty-cycle from 0 to this value directly. 7.6.3.47 fanpwm3 stop duty-cycle ? index 82h bit name r/w default description 7-0 f3_stop_duty r/w 25h fanpwm3 will decreasing duty-cyc le to 0 from this value directly or keep duty-cycle in this value when f3_keep_stop set to 1. 7.6.3.48 fanpwm3 output frequency control ? index 83h bit name r/w default description 7 pwm3_div[7] r/w set to 1, pr eclk(pre-clock) = 48m hz ; set to 0, preclk = 1m hz . 6-0 pwm3_div[6:0] r/w 80h pre-divisor of preclk. fanpwm3 output frequency = 256 ) (pr ? ? divisor e preclk so, pwm frequency ranges from 30.5hz~187.5khz 7.6.3.49 fanpwm3 step contro l register -- index 84h bit name r/w default description
july, 2007 v0.26p 80 f71806 7-4 f3_up_step r/w this value determines the increasing speed of pwm3_duty. 3-0 f3_down_step r/w 00h this value determines the decreasing speed of pwm3_duty 7.6.3.50 fan3_fault time register ? index 85h bit name r/w default description 7-0 f3_fault_time r/w 03h this register determines the time for fan to chase to the expect speed. two conditions cause fan fault event: (1). when pwm_duty reaches ffh, if the fan speed count can?t reach the fan expect count in the time. (2). when pwm_duty reaches 00h, if t he fan speed count can?t reach the fan expect count in the time. the unit of this register is 1 sec ond. the default value is 180 seconds. 7.6.3.51 fan3 expect c ount register-- index 89h bit name r/w default description 7-4 reserved - 3-0 f3_expect (msb) r 00h user expect fan3 count value, program th is register to control the expect fan3 speed 7.6.3.52 fan3 expect c ount register-- index 8ah bit name r/w default description 7-0 f3_expect (lsb) r 00h user expect fan3 count value, program this register to control the expect fan3 speed. 7.6.3.53 fan3 pwm_duty -- index 8bh bit name r/w default description 7-0 pwm_duty3 r/w ffh when fan3 control is at pw m duty-cycle mode, this value represents the duty-cycle. when fan3 control is at dc mode, th is value represents the dc voltage output. each step (lsb) is vcc / 256. this register is programmable at manual mode. at speed or temperature mode, th is register reflects current fanpwm1 duty-cycle 7.6.3.54 fan1 control v. s. temperature 1 (index a0 -- ad registers ) t1 boundary 1 temperature ? index a0h bit name r/w default description
july, 2007 v0.26p 81 f71806 7-0 t1_tp_1 r/w 00h the 1 st boundary temperature for t1 in temperature mode. when t1 temperature is exceed this boundary, fan1 segment 1 speed count registers will be loaded into fan1 expect count registers. when t1 temperature is below this boundary, fan1 segment 2 speed count registers will be loaded into fan1 expect count registers. t1 boundary 5 temperature ? index a1h bit name r/w default description 7-0 t1_tp_5 r/w 00h the 5th boundary temp erature for t1 in temperature mode. when t1 temperature is exceed this boundary, fan1 segment 5 speed count registers will be loaded into fan1 expect count registers. when t1 temperature is below this boundary, fan1 segment 6 speed count registers will be loaded into fan1 expect count registers. t1 boundary 9 temperature ? index a2h bit name r/w default description 7-0 t1_tp_9 r/w 00h the 9th boundary temp erature for t1 in temperature mode. when t1 temperature is exceed this boundary, fan1 segment 9 speed count registers will be loaded into fan1 expect count registers. when t1 temperature is below this boundary, fan1 segment 10 speed count registers will be loaded into fan1 expect count registers. fan1 segment 1 speed count (msb) ? index a4h bit name r/w default description 7-4 reserved - 3-0 t1_sp_1_msb r/w 0fh the msb of 1st expected fan speed for fan1 in temperature mode. fan1 segment 1 speed count (lsb) ? index a5h bit name r/w default description 7-0 t1_sp_1_lsb r/w ffh the lsb of 1st expected fan speed for fan1 in temperature mode. fan1 segment 5 speed count (msb) ? index a6h bit name r/w default description 7-4 reserved - 3-0 t1_sp_5_msb r/w 0fh the msb of 5th expected fan speed for fan1 in temperature mode. fan1 segment 5 speed count (lsb) ? index a7h bit name r/w default description 7-0 t1_sp_5_lsb r/w ffh the lsb of 5th expected fan speed for fan1 in temperature mode.
july, 2007 v0.26p 82 f71806 fan1 segment 9 speed count (msb) ? index a8h bit name r/w default description 7-4 reserved - 3-0 t1_sp_9_msb r/w 0fh the msb of 9th expected fan speed for fan1 in temperature mode. fan1 segment 9 speed count (lsb) ? index a9h bit name r/w default description 7-0 t1_sp_9_lsb r/w ffh the lsb of 9th expected fan speed for fan1 in temperature mode. 7.6.3.55 fan2 control v. s. temperature 2 (index b0 -- bd registers ) t2 boundary 1 temperature ? index b0h bit name r/w default description 7-0 t2_tp_1 r/w 00h the 1 st boundary temperature for t2 in temperature mode. when t2 temperature is exceed this boundary, fan2 segment 1 speed count registers will be loaded into fan2 expect count registers. when t2 temperature is below this boundary, fan2 segment 2 speed count registers will be loaded into fan2 expect count registers. t2 boundary 5 temperature ? index b1h bit name r/w default description 7-0 t2_tp_5 r/w 002h the 5th boundary temp erature for t2 in temperature mode. when t2 temperature is exceed this boundary, fan2 segment 5 speed count registers will be loaded into fan2 expect count registers. when t2 temperature is below this boundary, fan2 segment 6 speed count registers will be loaded into fan2 expect count registers. t2 boundary 9 temperature ? index b2h bit name r/w default description 7-0 t2_tp_9 r/w 00h the 9th boundary temp erature for t2 in temperature mode. when t2 temperature is exceed this boundary, fan2 segment 9 speed count registers will be loaded into fan2 expect count registers. when t2 temperature is below this boundary, fan2 segment 10 speed count registers will be loaded into fan2 expect count registers. fan2 segment 1 speed count (msb) ? index b4h bit name r/w default description 7-4 reserved - 3-0 t2_sp_1_msb r/w 0fh the msb of 1st expected fan speed for fan2 in temperature mode.
july, 2007 v0.26p 83 f71806 fan2 segment 1 speed count (lsb) ? index b5h bit name r/w default description 7-0 t2_sp_1_lsb r/w ffh the lsb of 1st expected fan speed for fan2 in temperature mode. fan2 segment 5 speed count (msb) ? index b6h bit name r/w default description 7-4 reserved - 3-0 t2_sp_5_msb r/w 0fh the msb of 5th expected fan speed for fan2 in temperature mode. fan2 segment 5 speed count (lsb) ? index b7h bit name r/w default description 7-0 t2_sp_5_lsb r/w ffh the lsb of 5th expected fan speed for fan2 in temperature mode. fan2 segment 9 speed count (msb) ? index b8h bit name r/w default description 7-4 reserved - 3-0 t2_sp_9_msb r/w 0fh the msb of 9th expected fan speed for fan2 in temperature mode. fan2 segment 9 speed count (lsb) ? index b9h bit name r/w default description 7-0 t2_sp_9_lsb r/w ffh the lsb of 9th expected fan speed for fan2 in temperature mode. 7.6.3.56 fan3 control v. s. temperature 3 ( index c0 -- cd registers ) t3 boundary 1 temperature ? index c0h bit name r/w default description 7-0 t3_tp_1 r/w 00h the 1 st boundary temperature for t3 in temperature mode. when t3 temperature is exceed this boundary, fan3 segment 1 speed count registers will be loaded into fan3 expect count registers. when t3 temperature is below this boundary, fan3 segment 2 speed count registers will be loaded into fan3 expect count registers. t3 boundary 5 temperature ? index c1h bit name r/w default description
july, 2007 v0.26p 84 f71806 7-0 t3_tp_5 r/w 00h the 5th boundary temp erature for t3 in temperature mode. when t3 temperature is exceed this boundary, fan3 segment 5 speed count registers will be loaded into fan3 expect count registers. when t3 temperature is below this boundary, fan3 segment 6 speed count registers will be loaded into fan3 expect count registers. t3 boundary 9 temperature ? index c2h bit name r/w default description 7-0 t3_tp_9 r/w 00h the 9th boundary temp erature for t3 in temperature mode. when t3 temperature is exceed this boundary, fan3 segment 9 speed count registers will be loaded into fan3 expect count registers. when t3 temperature is below this boundary, fan3 segment 10 speed count registers will be loaded into fan3 expect count registers. fan3 segment 1 speed count (msb) ? index c4h bit name r/w default description 7-4 reserved - 3-0 t3_sp_1_msb r/w 0fh the msb of 1st expected fan speed for fan3 in temperature mode. fan3 segment 1 speed count (lsb) ? index c5h bit name r/w default description 7-0 t3_sp_1_lsb r/w ffh the lsb of 1st expected fan speed for fan3 in temperature mode. fan3 segment 5 speed count (msb) ? index c6h bit name r/w default description 7-4 reserved - 3-0 t3_sp_5_msb r/w 0fh the msb of 5th expected fan speed for fan3 in temperature mode. fan3 segment 5 speed count (lsb) ? index c7h bit name r/w default description 7-0 t3_sp_5_lsb r/w ffh the lsb of 5th expected fan speed for fan1 in temperature mode. fan3 segment 9 speed count (msb) ? index c8h bit name r/w default description 7-4 reserved - 3-0 t3_sp_9_msb r/w 0fh the msb of 9th expected fan speed for fan3 in temperature mode. fan3 segment 9 speed count (lsb) ? index c9h bit name r/w default description
july, 2007 v0.26p 85 f71806 7-0 t3_sp_9_lsb r/w ffh the lsb of 9th expected fan speed for fan3 in temperature mode. 7.7 gpio registers 7.7.1 logic device number register logic device number register ? index 07h bit name r/w default description 7-0 ldn r/w 00h 00h: select fdc dev ice configuration registers. 01h: select uart 1 device configuration registers. 02h: select uart 2 device configuration registers. 03h: select parallel port devic e configuration registers. 04h: select hardware monitor device configuration registers. 05h: reserved. 06h: select gpio device c onfiguration registers. 07h: select vid device c onfiguration registers. 0ah: select pme & acpi device configuration registers. 7.7.2 configuration registers 7.7.2.1 irq channel select register ? index 70h bit name r/w default description 7-4 reserved - - reserved. 3-0 selgioirq r/w 0h select the irq channel for gpio[6:0] interrupt. 7.7.2.2 gpio output enable register ? index e0h bit name r/w default description 7 reserved - - reserved. 6 gpio6_oe r/w 0 0: gpio6 is in input mode. 1: gpio6 is in output mode. 5 gpio5_oe r/w 0 0: gpio5 is in input mode. 1: gpio5 is in output mode. 4 gpio4_oe r/w 0 0: gpio4 is in input mode. 1: gpio4 is in output mode.
july, 2007 v0.26p 86 f71806 3 gpio3_oe r/w 0 0: gpio3 is in input mode. 1: gpio3 is in output mode. 2 gpio2_oe r/w 0 0: gpio2 is in input mode. 1: gpio2 is in output mode. 1 gpio1_oe r/w 0 0: gpio1 is in input mode. 1: gpio1 is in output mode. 0 gpio0_oe r/w 0 0: gpio0 is in input mode. 1: gpio0 is in output mode. 7.7.2.3 gpio output data register ? index e1h bit name r/w default description 7 reserved - - reserved. 6 gpio6_val r/w 0 0: gpio6 out puts 0 when in output mode. 1: gpio6 outputs1 when in output mode and gpio6_mode is 0. gpio6 outputs a pulse when in output mode and gpio6_mode is 1. auto clear after the pulse. 5 gpio5_val r/w 0 0: gpio5 out puts 0 when in output mode. 1: gpio5 outputs 1 when in out put mode and gpio5_mode is 0. gpio5 outputs a pulse when in output mode and gpio5_mode is 1. auto clear after the pulse. 4 gpio4_val r/w 0 0: gpio4 out puts 0 when in output mode. 1: gpio4 outputs 1 when in out put mode and gpio4_mode is 0. gpio4 outputs a pulse when in output mode and gpio4_mode is 1. auto clear after the pulse. 3 gpio3_val r/w 0 0: gpio3 out puts 0 when in output mode. 1: gpio3 outputs 1 when in out put mode and gpio3_mode is 0. gpio3 outputs a pulse when in output mode and gpio3_mode is 1. auto clear after the pulse. 2 gpio2_val r/w 0 0: gpio2 out puts 0 when in output mode. 1: gpio2 outputs 1 when in out put mode and gpio2_mode is 0. gpio2 outputs a pulse when in output mode and gpio2_mode is 1. auto clear after the pulse. 1 gpio1_val r/w 0 0: gpio1 out puts 0 when in output mode. 1: gpio1 outputs 1 when in out put mode and gpio1_mode is 0. gpio1 outputs a pulse when in output mode and gpio1_mode is 1. auto clear after the pulse. 0 gpio0_val r/w 0 0: gpio0 out puts 0 when in output mode. 1: gpio0 outputs 1 when in out put mode and gpio0_mode is 0. gpio0 outputs a pulse when in output mode and gpio0_mode is 1. auto clear after the pulse. 7.7.2.4 gpio pin st atus register ? index e2h bit name r/w default description 7 reserved - - reserved. 6 gpio6_in r - the pin status of gpio6/voltage_fault4#/wdtrst1#. 5 gpio5_in r - the pin status of gpio5/voltage_fault3#.
july, 2007 v0.26p 87 f71806 4 gpio4_in r - the pin status of gpio4/voltage_fault2#. 3 gpio3_in r - the pin status of gpio3/voltage_fault1#. 2 gpio2_in r - the pin status of gpio2. 1 gpio1_in r - the pin status of gpio1. 0 gpio0_in r - the pin status of gpio0. 7.7.2.5 gpio output mode register ? index e3h bit name r/w default description 7 reserved - - reserved. 6 gpio6_mode r/w 0 0: level mode, gpio6 output is controlled by gpio6_val. 1: pulse mode, write gpio6_val 1 to generate a pulse via gpio6. 5 gpio5_mode r/w 0 0: level mode, gpio5 output is controlled by gpio5_val. 1: pulse mode, write gpio5_val 1 to generate a pulse via gpio5. 4 gpio4_mode r/w 0 0: level mode, gpio4 output is controlled by gpio4_val. 1: pulse mode, write gpio4_val 1 to generate a pulse via gpio4. 3 gpio3_mode r/w 0 0: level mode, gpio3 output is controlled by gpio3_val. 1: pulse mode, write gpio3_val 1 to generate a pulse via gpio3. 2 gpio2_mode r/w 0 0: level mode, gpio2 output is controlled by gpio2_val. 1: pulse mode, write gpio2_val 1 to generate a pulse via gpio2. 1 gpio1_mode r/w 0 0: level mode, gpio1 output is controlled by gpio1_val. 1: pulse mode, write gpio1_val 1 to generate a pulse via gpio1. 0 gpio0_mode r/w 0 0: level mode, gpio0 output is controlled by gpio0_val. 1: pulse mode, write gpio0_val 1 to generate a pulse via gpio0. 7.7.2.6 gpio pulse widt h select 1 register ? index e4h bit name r/w default description 7-6 gpio3_pw_sel r/w 00 gpio3 pulse width select: 00: 500us (default). 01: 1ms. 10: 20ms. 11: 100ms. 5-4 gpio2_pw_sel r/w 00 gpio2 pulse width select: 00: 500us (default). 01: 1ms. 10: 20ms. 11: 100ms. 3-2 gpio1_pw_sel r/w 00 gpio1 pulse width select: 00: 500us (default). 01: 1ms. 10: 20ms. 11: 100ms.
july, 2007 v0.26p 88 f71806 1-0 gpio0_pw_sel r/w 00 gpio0 pulse width select: 00: 500us (default). 01: 1ms. 10: 20ms. 11: 100ms. 7.7.2.7 gpio pulse widt h select 2 register ? index e5h bit name r/w default description 7-6 reserved - - reserved. 5-4 gpio6_pw_sel r/w 00 gpio6 pulse width select: 00: 500us (default). 01: 1ms. 10: 20ms. 11: 100ms. 3-2 gpio5_pw_sel r/w 00 gpio5 pulse width select: 00: 500us (default). 01: 1ms. 10: 20ms. 11: 100ms. 1-0 gpio4_pw_sel r/w 00 gpio4 pulse width select: 00: 500us (default). 01: 1ms. 10: 20ms. 11: 100ms. 7.7.2.8 gpio pulse mode register ? index e6h bit name r/w default description 7 reserved - - reserved. 6 gpio6_pul_mode r/w 0 gpio6 pulse mode: 0: output low pulse when in pulse mode. 1: output high pulse when in pulse mode. 5 gpio5_pul_mode r/w 0 gpio5 pulse mode: 0: output low pulse when in pulse mode. 1: output high pulse when in pulse mode. 4 gpio4_pul_mode r/w 0 gpio4 pulse mode: 0: output low pulse when in pulse mode. 1: output high pulse when in pulse mode. 3 gpio3_pul_mode r/w 0 gpio3 pulse mode: 0: output low pulse when in pulse mode. 1: output high pulse when in pulse mode. 2 gpio2_pul_mode r/w 0 gpio2 pulse mode: 0: output low pulse when in pulse mode. 1: output high pulse when in pulse mode.
july, 2007 v0.26p 89 f71806 1 gpio1_pul_mode r/w 0 gpio1 pulse mode: 0: output low pulse when in pulse mode. 1: output high pulse when in pulse mode. 0 gpio0_pul_mode r/w 0 gpio0 pulse mode: 0: output low pulse when in pulse mode. 1: output high pulse when in pulse mode. 7.7.2.9 gpio pad type register ? index e7h bit name r/w default description 7 reserved - - reserved. 6 gpio6_drv_en r/w 0 gpio6 pad type: 0: open drain. 1: push-pull. 5 gpio5_drv_en r/w 0 gpio5 pad type: 0: open drain. 1: push-pull. 4 gpio4_drv_en r/w 0 gpio4 pad type: 0: open drain. 1: push-pull. 3 gpio3_drv_en r/w 0 gpio3 pad type: 0: open drain. 1: push-pull. 2 gpio2_drv_en r/w 0 gpio2 pad type: 0: open drain. 1: push-pull. 1 gpio1_drv_en r/w 0 gpio1 pad type: 0: open drain. 1: push-pull. 0 gpio0_drv_en r/w 0 gpio0 pad type: 0: open drain. 1: push-pull. 7.7.2.10 gpio irq enable register ? index e8h bit name r/w default description 7 reserved - - reserved. 6 gpio6_irq_en r/w 0 gpio6 interrupt enable: 0: disable interrupt. 1: assert an interrupt when gpio6 changed in input mode. 5 gpio5_irq_en r/w 0 gpio5 interrupt enable: 0: disable interrupt. 1: assert an interrupt when gpio5 changed in input mode. 4 gpio4_irq_en r/w 0 gpio4 interrupt enable: 0: disable interrupt. 1: assert an interrupt when gpio4 changed in input mode.
july, 2007 v0.26p 90 f71806 3 gpio3_irq_en r/w 0 gpio3 interrupt enable: 0: disable interrupt. 1: assert an interrupt when gpio3 changed in input mode. 2 gpio2_irq_en r/w 0 gpio2 interrupt enable: 0: disable interrupt. 1: assert an interrupt when gpio2 changed in input mode. 1 gpio1_irq_en r/w 0 gpio1 interrupt enable: 0: disable interrupt. 1: assert an interrupt when gpio1 changed in input mode. 0 gpio0_irq_en r/w 0 gpio0 interrupt enable: 0: disable interrupt. 1: assert an interrupt when gpio0 changed in input mode. 7.7.2.11 gpio edge detect register ? index e9h bit name r/w default description 7 reserved - - reserved. 6 gpio6_edg r/w 1 gpio6 edge detect: 0: input data does not change. 1: input data changes. write 1 to clear. 5 gpio5_edg r/w 1 gpio5 edge detect: 0: input data does not change. 1: input data changes. write 1 to clear. 4 gpio4_edg r/w 1 gpio4 edge detect: 0: input data does not change. 1: input data changes. write 1 to clear. 3 gpio3_edg r/w 1 gpio3 edge detect: 0: input data does not change. 1: input data changes. write 1 to clear. 2 gpio2_edg r/w 1 gpio2 edge detect: 0: input data does not change. 1: input data changes. write 1 to clear. 1 gpio1_edg r/w 1 gpio1 edge detect: 0: input data does not change. 1: input data changes. write 1 to clear. 0 gpio0_edg r/w 1 gpio0 edge detect: 0: input data does not change. 1: input data changes. write 1 to clear. 7.7.2.12 gpio1 output enable register ? index f0h bit name r/w default description 7 reserved - - reserved. 6 gpio16_oe r/w 0 0: gpio16 is in input mode. 1: gpio16 is in output mode. 5 gpio15_oe r/w 0 0: gpio15 is in input mode. 1: gpio15 is in output mode.
july, 2007 v0.26p 91 f71806 4 gpio14_oe r/w 0 0: gpio14 is in input mode. 1: gpio14 is in output mode. 3 gpio13_oe r/w 0 0: gpio13 is in input mode. 1: gpio13 is in output mode. 2 gpio12_oe r/w 0 0: gpio12 is in input mode. 1: gpio12 is in output mode. 1 gpio11_oe r/w 0 0: gpio11 is in input mode. 1: gpio11 is in output mode. 0 gpio10_oe r/w 0 0: gpio10 is in input mode. 1: gpio10 is in output mode. 7.7.2.13 gpio1 output data register ? index f1h bit name r/w default description 7 reserved - - reserved. 6 gpio16_val r/w 1 0: gpio16 out puts 0 when in output mode. 1: gpio16 outputs1 when in output mode. 5 gpio15_val r/w 1 0: gpio15 out puts 0 when in output mode. 1: gpio15 outputs 1 when in output mode. 4 gpio14_val r/w 1 0: gpio14 out puts 0 when in output mode. 1: gpio14 outputs 1 when in output mode. 3 gpio13_val r/w 1 0: gpio13 out puts 0 when in output mode. 1: gpio13 outputs 1 when in output mode. 2 gpio12_val r/w 1 0: gpio12 out puts 0 when in output mode. 1: gpio12 outputs 1 when in output mode. 1 gpio11_val r/w 1 0: gpio11 outputs 0 when in output mode. 1: gpio11 outputs 1 when in output mode. 0 gpio10_val r/w 1 0: gpio10 out puts 0 when in output mode. 1: gpio10 outputs 1 when in output mode. 7.7.2.14 gpio1 pin status register ? index f2h bit name r/w default description 7 reserved - - reserved. 6 gpio16_in r - the pin status of irtx/gpio16. 5 gpio15_in r - the pin stat us of pcirst5#/gpio15. 4 gpio14_in r - the pin stat us of pcirst3#/gpio14. 3 gpio13_in r - the pin stat us of pcirst2#/gpio13. 2 gpio12_in r - the pin stat us of pwrok1/gpio12. 1 gpio11_in r - the pin status of pcirst1#/gpio11. 0 gpio10_in r - the pin stat us of rstcon#/gpio10. 7.7.2.15 gpio2 output enable register ? index f3h bit name r/w default description
july, 2007 v0.26p 92 f71806 7 gpio27_oe r/w 0 0: gpio27 is in input mode. 1: gpio27 is in output mode. 6 gpio26_oe r/w 0 0: gpio26 is in input mode. 1: gpio26 is in output mode. 5 gpio25_oe r/w 0 0: gpio25 is in input mode. 1: gpio25 is in output mode. 4 gpio24_oe r/w 0 0: gpio24 is in input mode. 1: gpio24 is in output mode. 3 gpio23_oe r/w 0 0: gpio23 is in input mode. 1: gpio23 is in output mode. 2 gpio22_oe r/w 0 0: gpio22 is in input mode. 1: gpio22 is in output mode. 1 gpio21_oe r/w 0 0: gpio21 is in input mode. 1: gpio21 is in output mode. 0 gpio20_oe r/w 0 0: gpio20 is in input mode. 1: gpio20 is in output mode. 7.7.2.16 gpio2 output data register ? index f4h bit name r/w default description 7 gpio27_val r/w 1 0: gpio27 out puts 0 when in output mode. 1: gpio27 outputs1 when in output mode. 6 gpio26_val r/w 1 0: gpio26 out puts 0 when in output mode. 1: gpio26 outputs1 when in output mode. 5 gpio25_val r/w 1 0: gpio25 out puts 0 when in output mode. 1: gpio25 outputs 1 when in output mode. 4 gpio24_val r/w 1 0: gpio24 out puts 0 when in output mode. 1: gpio24 outputs 1 when in output mode. 3 gpio23_val r/w 1 0: gpio23 out puts 0 when in output mode. 1: gpio23 outputs 1 when in output mode. 2 gpio22_val r/w 1 0: gpio22 out puts 0 when in output mode. 1: gpio22 outputs 1 when in output mode. 1 gpio21_val r/w 1 0: gpio21 out puts 0 when in output mode. 1: gpio21 outputs 1 when in output mode. 0 gpio20_val r/w 1 0: gpio20 out puts 0 when in output mode. 1: gpio20 outputs 1 when in output mode. 7.7.2.17 gpio2 pin status register ? index f5h bit name r/w default description 7 gpio27_in r - the pin stat us of rsmrst#/gpio27. 6 gpio26_in r - the pin stat us of pcirst4#/gpio26. 5 gpio25_in r - the pin stat us of pwrok2/gpio25. 4 gpio24_in r - the pin status of gpio24/ovt#/wdtrst2#. 3 gpio23_in r - the pin st atus of pson#/gpio23. 2 gpio22_in r - the pin status of pwswin#/gpio22.
july, 2007 v0.26p 93 f71806 1 gpio21_in r - the pin status of pme#/gpio21. 0 gpio20_in r - the pin status of pwswout#/gpio20. 7.7.2.18 gpio3 output enable register ? index f6h bit name r/w default description 7-2 reserved - - reserved. 1 gpio31_oe r/w 0 0: gpio31 is in input mode. 1: gpio31 is in output mode. 0 gpio30_oe r/w 0 0: gpio30 is in input mode. 1: gpio30 is in output mode. 7.7.2.19 gpio3 output data register ? index f7h bit name r/w default description 7-2 reserved - - reserved. 1 gpio31_val r/w 1 0: gpio31 out puts 0 when in output mode. 1: gpio31 outputs 1 when in output mode. 0 gpio30_val r/w 1 0: gpio30 out puts 0 when in output mode. 1: gpio30 outputs 1 when in output mode. 7.7.2.20 gpio3 pin status register ? index f8h bit name r/w default description 7-2 reserved - - reserved. 1 gpio31_in r - the pin st atus of s3#/gpio31. 0 gpio30_in r - the pin st atus of irrx/gpio30. 7.8 vid register 7.8.1 logic device number register logic device number register ? index 07h bit name r/w default description
july, 2007 v0.26p 94 f71806 7-0 ldn r/w 00h 00h: select fdc dev ice configuration registers. 01h: select uart 1 device configuration registers. 02h: select uart 2 device configuration registers. 03h: select parallel port devic e configuration registers. 04h: select hardware monitor device configuration registers. 05h: reserved. 06h: select gpio device c onfiguration registers. 07h: select vid device c onfiguration registers. 0ah: select pme & acpi device configuration registers. 7.8.2 vid configur ation registers vid device enable register ? index 30h bit name r/w default description 7-1 reserved - 0 reserved 0 vid_en r/w 0 0: disable vid. 1: enable vid. base address high register ? index 60h bit name r/w default description 7-0 base_addr_hi r/w 00h the msb of vid base address. base address low register ? index 61h bit name r/w default description 7-0 base_addr_lo r/w 00h the lsb of vid base address. 7.8.3 device registers 7.8.3.1 vid control register ? index 00h bit name r/w default description 7 clk_sel r/w 0 select watchdog timer clock, set to 1 will use external clock source (power by vcc), else will use internal osc 2mhz clock (power by vsb3v). 6-3 reserved - - reserved
july, 2007 v0.26p 95 f71806 2 cpu_sel r/w 0 cpu select, if set this bit to 1 will select amd cpu, else if set to 0 is intel cpu(default), (this bit will auto clear by slotocc# or watchdog timer, and protect write command by vid_key reg 0x30.) 1 en_otf r/w 0 if set this bit to 1 will enable vid on the fly mode, user can change new vid value by program the reg 0x01 vid_off set, else if set to 0, vid will in programming mode, user can program reg 0x02 to decide vid output data. (this bit will auto clear by slotocc# or watchdog timer, and protect write command by vid_key reg 0x03.) 0 vid_extend r/w 1 set this bit to 1 to enable intel vrm10 mode, this bit default is enable, (this bit will auto clear by slotocc# or watchdog timer, and protect write command by vid_key reg 0x03.) 7.8.3.2 vid on the fl y offset register ? index 01h bit name r/w default description 7-6 reserved - - reserved 5-0 vid_offset r/w 00h vid offset register. the offset value is representative in 2?s complement. the real vid value will be added by this offs et and then will be put into vid_out (when en_otf is set). the offset ranges from -16 to +31. 1fh : +31. 01h : +1. 00h : +0. 3fh : -1. 30h : -16. 7.8.3.3 vid output data register ? index 02h bit name r/w default description 7 en_vidout r/w 0 enable vidout. if set to one and vid output key is asserted referred as vidkey, the vidout_data will output to these pins of vidout. this bit is supplied by vsb3v and reset by the vsb3v power good or watchdog timer is asserted or slotocc# is asserted. 6 vidkey_ok ro 0 when the sequential key is programmed to regi ster 22h. this bit will set to 1. if program exit sequential key to register 22h, this bit read back will be 0 5-0 vidout_data r/w 00h vidout data. these bits is mapping to vidout[5:0] if en_vidout is enable. these bits power is supplied by vsb3v for keeping data when vdd3v power is lose.
july, 2007 v0.26p 96 f71806 7.8.3.4 vidke y protection ? index 03h bit name r/w default description 7-0 vidkey r/w 00h vid key for protection the vidout. if wo uld like to program vid output data register, the sequential key should be programmed first. the vid output register is disable in the default ( vsb3v power on). the sequential keys are defined as 0x32, 0x5d, 0x42, 0xac. and the exit key is 0x35. 7.8.3.5 vid input data register ? index 04h bit name r/w default description 7-6 reserved - - reserved 5-0 vid_in r xxh vid input data. 7.8.3.6 watchdog timer control register ? index 05h bit name r/w default description 7 reserved r 0 reserved. read will return 0. 6 sts_wd_tmout r / w 0 watchdog is timeout. when the watchdog is timeout, this bit will be set to one. if set to 1, write 1 will clear this bit. write 0, no effect. 5 wd_enable r/w 0 enable watchdog timer. 4 wd_pulse r/w 0 watchdog output level or pulse. if set 0 ( default), the pin of watchdog is level output. if write 1, the pin wi ll output with a pulse. 3 wd_unit r/w 0 watchdog unit select. default 0 is sele ct second. write 1 to select minute. 2 wd_hactive r/w 0 program wd output level. if set to 1 and watchdog asserted, the pin will be high. if set to 0 and watchdog asserted, this pin will drive low (default). 1-0 wd_pswidth r/w 00 watchdog pulse width selection. if the pi n output is selected to pulse mode. the pulse width can be choice. 00b ? 1m second. 01b ? 25m second. 10b ? 125m second 11b ? 5 second 7.8.3.7 watchdog timer range register ? index 05h bit name r/w default description 7-0 wd_time r/w 00h watchdog timing range from 0 ~ 255. the unit is either second or minute programmed by the watchdog timer control register bit3.
july, 2007 v0.26p 97 f71806 7.9 acpi and pme registers 7.9.1 logic device number register logic device number register ? index 07h bit name r/w default description 7-0 ldn r/w 00h 00h: select fdc dev ice configuration registers. 01h: select uart 1 device configuration registers. 02h: select uart 2 device configuration registers. 03h: select parallel port devic e configuration registers. 04h: select hardware monitor device configuration registers. 05h: reserved. 06h: select gpio device c onfiguration registers. 07h: select vid device c onfiguration registers. 0ah: select pme & acpi device configuration registers. 7.9.2 acpi and pme conf iguration registers device enable register ? index 30h bit name r/w default description 7-1 reserved - - reserved 0 pme_en r/w 0 0: disable pme. 1: enable pme. pme event enable register ? index f0h bit name r/w default description 7 reserved - - reserved 6 ms_pme_en r/w 0 ps/2 mouse pme event enable. 0: disable ps/2 mouse pme event. 1: enable ps/2 mouse pme event. 5 reserved. -* 0 reserved. 4 hm_pme_en r/w 0 hardware monitor pme event enable. 0: disable hardware monitor pme event. 1: enable hardware monitor pme event.
july, 2007 v0.26p 98 f71806 3 prt_pme_en r/w 0 parallel port pme event enable. 0: disable parallel port pme event. 1: enable parallel port pme event. 2 ur2_pme_en r/w 0 uart 2 pme event enable. 0: disable uart 2 pme event. 1: enable uart 2 pme event. 1 ur1_pme_en r/w 0 uart 1 pme event enable. 0: disable uart 1 pme event. 1: enable uart 1 pme event. 0 fdc_pme_en r/w 0 fdc pme event enable. 0: disable fdc pme event. 1: enable fdc pme event. pme event status register ? index f1h bit name r/w default description 7 reserved - - reserved 6 ms_pme_st r/w 1 ps/2 mouse pme event status. 0: ps/2 mouse has no pme event. 1: ps/2 mouse has a pme event to asser t. write 1 to clear to be ready for next pme event. 5 reserved. - 1 reserved. 4 hm_pme_st r/w 0 hardware monitor pme event status. 0: hardware monitor has no pme event. 1: hardware monitor has a pme event to assert. write 1 to clear to be ready for next pme event. 3 prt_pme_st r/w 0 parallel port pme event status. 0: parallel port has no pme event. 1: parallel port has a pme event to assert. write 1 to clear to be ready for next pme event. 2 ur2_pme_st r/w 0 uart 2 pme event status. 0: uart 2 has no pme event. 1: uart 2 has a pme event to assert. write 1 to clear to be ready for next pme event. 1 ur1_pme_st r/w 0 uart 1 pme event status. 0: uart 1 has no pme event. 1: uart 1 has a pme event to assert. write 1 to clear to be ready for next pme event. 0 fdc_pme_st r/w 1 fdc pme event status. 0: fdc has no pme event. 1: fdc has a pme event to assert. write 1 to clear to be ready for next pme event. acpi control register ? index f4h bit name r/w default description 7-3 reserved - - reserved
july, 2007 v0.26p 99 f71806 2-1 pwrctrl r/w 11 the acpi control the pson_n to always on or always off or keep last state 00 : keep last state 10 : always on 01 : reserved (always on) 11: always off 0 vsb_pwr_loss r/w 0 when vsb 3v comes, it will set to 1, and write 1 to clear it acpi control register ? index f5h bit name r/w default description 7 soft_rst_acpi r/w 0 software reset to acpi (auto clear after reset) 6 reserved - - reserved 5 rstcon_en r/w 1 set to 1 to enable rstcon_en to pcirst, set to 0 to enable rstcon_en to pwokin1 and pwokin2 4-3 delay r/w 11 the pwrok delay timing from vdd3vok by followed setting 00 : 100ms 01 : 200ms 10 : 300ms 11 : 400ms 2 vindb_en r/w 1 enable the pcirstin_n and atxpwgd debounce 1 reserved - - reserved. 0 reserved - - reserved. 8 pcb layout guide f71806 adopts current mode measure method to do temperature detected. the measure data will not be affected by different process of cpu due to use current mode technology. this technology measures mini-voltage from the remote sensor so a good pcb layout must be cared about noise minimizing. the noises often come from circuit trace which is a track from remote sensor (cpu side) to detect circuit input (f71806 side). the signal on this track will be inducted mini-noises when it passes through a high electromagnetic area. those effects will result in the mini-noises and show in the detected side. it will be reported a wrong data which you want to measure. please pa y attention and follow up the check list below in order to get
july, 2007 v0.26p 100 f71806 an actual and real temperature inside the chip. 1. the d1+/d2+/d3+ and agnd (d-) tracks must not pass through/by pwm power-mos. keep as far as possible from power mos. 2. place a 0.1f bypass capacitor close to the v cc pin (pin# 99). place an external 2200pf input filter capacitors across d+, d- and close to the f71806. near the pin agnd (d-) must be placed a through hole into the gnd plane before connect to the external 2200pf capacitor. 3. place the f71806 as close as practical to the remote s ensor diode. in noisy environments, such as a computer main-board, the distance can be 4 to 8 inches. (typ). this l ength can be increased if the worst noise sources are avoided. noise sources generally inclu de clock generators, crts, memo ry buses and pci/isa bus etc. 4. separated route the d1+, d2+ or d3+ with agnd (d-) tra cks close together and in parallel after adding external 2200pf capacitor. for more reliable, it had better with grounded guard tracks on each side. provide a ground plane under the tracks if possible. do not route d+ & d- lines next to the defl ection coil of the crt. and al so don?t route the trace across fast digital signals which can easily induce bigger error. gnd gnd thermda(dxp) 10mils 10mils minimum 10mils thermdc(dxn) 10mils 5. use wide tracks to minimize inductance and reduce noise pickup. 10 mil track minimum width and spacing is recommended. 6. try to minimize the number of component/solder joints, called through hole, which can cause thermocouple effects. where through holes are used, make sure that they are in both the d+ and d- path and at the same temperature. thermocouple effects should not be a major problem as 1 corresponds to about 200v. it means that a copper j -solder thermocouple exhibits 3v/ , and takes about 200v of the voltage error at d+ & d j - to cause a 1 measurement error. j adding a few thermocouples causes a negligible error. 7. if the distance to the remote sensor is more than 8 inches, t he use of twisted pair cable is recommended. it will work up to vcc 99 d1+ agnd(d-) 89 86 2200pf f71872f 0.1uf from thermal diode thermda thermdc vcc 99 d1+ agnd(d-) 89 86 2200pf f71872f 0.1uf from thermal diode thermda thermdc f71806
july, 2007 v0.26p 101 f71806 around 6 to 12 feet. because the measurement technique uses switched current source s, excessive cable and/or filter capacitance will affect the measurement accuracy. when using long cables, the filter ca pacitor should be reduced or removed. cable resistance can also induce errors. for example: 1 ? series resistance introduces about 0.5 error. j 9 electrical characteristics 9.1 absolute maximum ratings parameter rating unit power supply voltage -0.5 to 5.5 v input voltage -0.5 to vdd+0.5 v operating temperature 0 to +70 c storage temperature -55 to 150 c note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device
july, 2007 v0.26p 102 f71806 9.2 dc characteristics (ta = 0 c to 70 c, vdd = 3.3v 10%, vss = 0v) (note) parameter sym. min. typ. max. unit conditions i/od 16ts - ttl level bi-directional pin, can select to od by register, with 16 ma source-sink capability input low threshold voltage vt- v vdd = 3.3 v input high threshold voltage vt+ v vdd = 3.3 v output low current iol ma vol = 0.4 v input high leakage ilih a vin = vdd input low leakage ilil a vin = 0v i/od 12ts - ttl level bi-directional pin, can select to od by register, with 12 ma source-sink capability input low threshold voltage vt- v vdd = 3.3 v input high threshold voltage vt+ v vdd = 3.3 v output low current iol ma vol = 0.4 v input high leakage ilih a vin = vdd input low leakage ilil a vin = 0v 9.3 ac characteristics serial bus timing parameter symbol min. max. unit scl clock period t - scl us start condition hold time t hd;sda us stop condition setup-up time t su;sto us data to scl setup time t su;dat ns data to scl hold time t hd;dat ns scl and sda rise time t r us scl and sda fall time t f ns
july, 2007 v0.26p 103 f71806 10 ordering information part number package type production flow F71806F 128-qfp(normal) commercial, 0 c to +70 c F71806Fg 128-qfp(green package) commercial, 0 c to +70 c 11 package dimensions feature integration technology inc. headquarters taipei office 3f-7, no 36, tai yuan st., bldg. k4, 7f, no.700, chung cheng rd., chupei city, hsinchu, taiwan 302, r.o.c. chungho city, taipei, taiwan 235, r.o.c. tel : 886-3-5600168 tel : 866-2-8227-8027 fax : 886-3-5600166 fax : 866-2-8227-8037 www: http://www.fintek.com.tw please note that all datasheet and specifications are subject to change without notice. all the trade marks of products and companies mentioned in this datasheet belong to their respective owne r
104 july , 2007 v0.26p 12 f71806 demo circuit densel# moa# index# drva# step# dir# wpt# rdata# wdata# wgate# tr k0# dskchg# hdsel# r16 4.7k pson# vcc3v pwswin# vsb5v r15 4.7k s1 switch c6 0.1u pwrok2 slotocc#_cpu 2 2 4 4 6 6 8 8 10 10 12 12 14 14 16 16 18 18 20 20 22 22 24 24 26 26 28 28 30 30 32 32 34 34 1 1 3 3 5 5 7 7 9 9 11 11 13 13 15 15 17 17 19 19 21 21 23 23 25 25 27 27 29 29 31 31 33 33 j1 header 17x2 1 2 3 4 5 6 7 8 rn4 4.7k-8p4r fanctl power control tit le size document number rev date: sheet of F71806F&fdd 0.1 feature integration technology inc. b 14 tuesday , october 19, 2004 pme# pwswout# init# vsb3v lad3 slotocc# 1 2 3 4 5 6 7 8 rn13 4.7k-8p4r sin2 pwswout# rsmrst# sout1 dtr2# hdsel# stb# lad2 ri1# step# pd5 ri2# index# fanctl3 vin7 pcirst5# dskchg# tr k0# d1+ vsb3v sout2 pme# dir# busy pwswin# vin3 fanin3 vidout4 clk_48m pd1 vcc1.2v slin# lad0 vidout2 drva# pcirst2# vidout3 cts2# afd# rdata# pd4 dsr1# fanctl2 fanin1 lad1 dcd1# pson# rts1# vin6 vcc3v ldrq# vid3 d2+ vidout0 dsr2# pcirst3# wdata# pd0 vin2 pd7 pwrok1 slct wpt# vidout1 pcirst4# pciclk ack# r76 4.7k vcc3v irtx vid2 copen# vid0 fanctl1 rsmrst# pd3 vin5 dtr1# d3+ moa# err# pwrok2 pcirst1# vidout5 cts1# sin1 dcd2# d- rts2# vin1 pcirst# pd6 lframe# serirq vref vbat densel# pe vin8 wgate# dtr2# 1 rts2# 2 dsr2# 3 vcc1 4 sout2 5 sin2 6 fanin1 7 fanctl1 8 fanin2 9 fanctl2 10 fanin3 11 fanctl3 12 vid5 13 vid4 14 gnd1 15 vid3 16 vid2 17 vid1 18 vid0 19 vidout5 20 vidout4 21 vidout3 22 vidout2 23 vidout1 24 vidout0 25 gpio0 26 gpio1 27 gpio2 28 gpio3 29 rstcon# 30 pcirst1# 31 pwrok1 32 pcirst2# 33 pcirst3# 34 vcc2 35 gpio4 36 lreset# 37 ldrq# 38 wpt# 64 index# 63 tr k0# 62 rdata# 61 wgate# 60 hdsel# 59 step# 58 dir# 57 wdata# 56 gpio6 55 drva# 54 gpio5 53 moa# 52 densel# 51 gnd2 50 clkin 49 pcirst5# 48 pciclk 47 nc 46 nc 45 lad3 44 lad2 43 lad1 42 lad0 41 lframe# 40 serirq 39 busy 102 pe 101 slct 100 vcc3 99 vin1 98 vin2 97 vin3 96 atxpg 95 vin5 94 vin6 93 vin7 92 pcirstin# 91 vref 90 d1+ 89 d2+ 88 d3+ 87 gnda 86 rsmrst# 85 pcirst4# 84 nc 83 nc 82 nc 81 nc 80 slot0cc# 79 pwrok2 78 gpio24 77 pson# 76 pwswin# 75 gnd3 74 pme# 73 pwswout# 72 s3# 71 irrx 70 vbat 69 copen# 68 vsb 67 irtx 66 dskchg# 65 ack# 103 slin# 104 init# 105 err# 106 afd# 107 stb# 108 pd0 109 pd1 110 pd2 111 pd3 112 pd4 113 pd5 114 pd6 115 pd7 116 gnd4 117 dcd1# 118 ri1# 119 cts1# 120 dtr1# 121 rts1# 122 dsr1# 123 sout1 124 sin1 125 dcd2# 126 ri2# 127 cts2# 128 F71806F u1 irrx fanin2 vid4 vid5 vin4 vid1 pd2 rstcon# s3# floppy conn. vid0 vid1 vid3 vid2 vid ctrl block vidout0 vidout1 vidout2 vidout3 pulled-high r q12 npn bce r2 1k r1 1k r3 1k r4 1k r5 1k vcc5v wpt# rdata# tr k0# index# dskchg# rstcon# r13 4.7k r11 4.7k vid5 vid4 c7 0.1u s2 switch r17 4.7k r12 4.7k r14 4.7k vidout5 vidout4 vcc3v 1 2 3 4 5 6 7 8 rn2 4.7k-8p4r pcirst5# pwrok1 vcc3v 1 2 3 4 5 6 7 8 rn5 4.7k-8p4r 1 2 c1 0.1u (place capacitor close to ic) vcc3v 1 2 c3 0.1uf slotocc# vcc3v vsb3v 1 2 c4 0.1u 1 2 c2 0.1u vcc3v 1 2 c5 0.1u vbat (gnd close to ic) vcc3v r10 4.7k r7 4.7k r8 4.7k r9 4.7k dtr2 sout2 dtr1 sout1 power trip r 1 2 3 4 5 6 7 8 rn1 4.7k-8p4r pcirst1# pcirst4# pcirst3# pcirst2# ( dtr1 must pull low )
105 july , 2007 v0.26p 1 2 3 4 jp1 4 header r30 0 r29 0 4fanctl 4fanctl fanctl r31 10k vcc5v r20 4.7k r22 27k r24 10k q1 pnp fanin1 r18 4.7k fanctl1 d1 1n4148 +12v r19 1k r23 330 + c8 10u c10 0.1u q3 mosf et n 2n7002 c15 0.1u r39 10k r36 27k r33 1k q5 pnp r32 4.7k r34 4.7k + c12 10u +12v 1 2 3 jp3 header 3 r38 330 fanctl2 q6 mosf et n 2n7002 d3 1n4148 fanin2 c19 0.1u r50 10k r47 27k r44 1k q8 pnp r43 4.7k r45 4.7k + c16 10u +12v 1 2 3 jp5 header 3 r48 330 fanctl3 q9 mosf et n 2n7002 d5 1n4148 fanin3 fanctl1 fanin1 tit le size document number rev date: sheet of fan control 0.1 feature integration technology inc. b 24 tuesday , october 19, 2004 pwm fan 3 speed control pwm fan 1 speed control the c10 is reserved for fan noise dis-bounce. the c13 is reserved for fan noise dis-bounce. pwm fan 2 speed control the c17 is reserved for fan noise dis-bounce. r28 3.9k r26 10k dc fan control with op 1 r40 10k 1 2 3 jp4 con3 fanctl2 r42 3.9k r41 10k d4 1n4148 5 6 7 8 4 + - u2b lm358 dc fan control with op 2 fanin2 r37 27k 12v r35 4.7k c13 47u q4 nds0605/sot c14 0.1u 12v q7 nds0605/sot r46 4.7k d6 1n4148 dc fan control with op 3 1 2 3 jp6 con3 12v fanin3 c18 0.1u fanctl3 c17 47u r52 10k r51 10k r53 3.9k r49 27k 3 2 1 8 4 + - u3a lm358 fan control for pwm or dc q2 nds0605/sot r25 27k 1 2 3 jp2 con3 r27 10k d2 1n4148 r21 4.7k c9 47u c11 0.1u 3 2 1 8 4 + - u2a lm358
106 july , 2007 v0.26p t rt2 thermistor 10k 1% d2+ r70 10k 1% vref (for system) t rt3 thermistor 10k 1% d3+ d- d- d- r64 10k vin6 vin7 r66 10k vcc5v vchipset +12v c22 3300p vin1 vin3 vin2 vin4 vin5 vin8 vin7 vin6 vin1 d3+ vin2 vin3 r57 47k r58 100k vin4 r60 200k r61 47k vin5 r62 200k r63 20k vin8 r67 200k r69 47k vref d- d1+ t rt1 thermistor 10k 1% r65 10k 1% r56 100k d1+ d3+ d2+ vsb5v r59 2m c23 1000p copen# 1 2 sw1 vbat copen# c21 3300p d2+ c20 3300p d+ d1+ q10 pnp 3906 q11 pnp 3906 tit le size document number rev date: sheet of hardware monitor 0.1 feature integration technology inc b 34 tuesday , october 19, 2004 the best voltage input level is about 1v. voltage sensing. vram vtt1.2v vcc1.5v vcore case open circuit r55 100k r54 10k from cpu diode sensing circuit (for system) thermistor sensing circuit for system temperature sensing for system r68 10k 1% (for system) vref
107 july , 2007 v0.26p 1 2 3 4 5 6 7 8 rn10 33-8p4r 1 2 3 4 5 6 7 8 rn11 33-8p4r 1 2 3 4 5 6 7 8 rn12 33-8p4r 1 2 3 4 5 6 7 8 rn7 2.7k-8p4r 1 2 3 4 5 6 7 8 rn9 2.7k-8p4r ack# vcc5v/3v pe init# busy slct slin# 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1 j2 db25 err# 1 2 3 4 5 6 7 8 rn8 2.7k-8p4r afd# 1 2 3 4 5 6 7 8 rn6 2.7k-8p4r stb# r71 2.7k pd1 pd2 pd0 pd4 pd5 pd3 pd7 pd6 ri1# cts1# dsr1# sin1 sout1 dcd1# rts1# dtr1# rin2 -12v ri2# dtrn2 dsrn2 rtsn2 vcc 20 da1 16 da2 15 da3 13 ry1 19 ry2 18 ry3 17 ry4 14 ry5 12 gnd 11 +12v 1 dy1 5 dy2 6 dy3 8 ra1 2 ra2 3 ra3 4 ra4 7 ra9 9 -12v 10 u5 cts2# ctsn2 sin2 sinn2 gnd vcc5v dtr2# soutn2 ctsn2 sout2 dcdn2 soutn2 dcdn2 sinn2 dsrn2 dsr2# rtsn2 5 9 4 8 3 7 2 6 1 p2 uart db9 rts2# dcd2# dtrn2 rin2 +12v 1 2 d7 1n5819 vcc5v tit le size document number rev date: sheet of printer &uart 0.1 feature integration technology inc. b 44 tuesday , october 19, 2004 c32 180p c31 180p parallel port interface c33 180p for lekage to power c24 180p c34 180p (female) c25 180p c35 180p dtrn1 dsrn1 sinn1 ctsn1 gnd rtsn1 dcdn1 1 2 3 4 5 jp7 header 5 vcc 20 da1 16 da2 15 da3 13 ry1 19 ry2 18 ry3 17 ry4 14 ry5 12 gnd 11 +12v 1 dy1 5 dy2 6 dy3 8 ra1 2 ra2 3 ra3 4 ra4 7 ra9 9 -12v 10 u4 c26 180p soutn1 ctsn1 dsrn1 dtrn1 dcdn1 5 9 4 8 3 7 2 6 1 p1 uart db9 sinn1 c36 180p rtsn1 soutn1 c27 180p c37 180p uart 1 port interface c28 180p uart 2 port interface c38 180p c29 180p c39 180p c30 180p c41 0.1u rin1 rin1 ir interface c40 180p -12v +12v vcc5v irrx irtx

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